Design and Verification Tools (DVT)

The Complete Development Environment for the e Language, SystemVerilog, and VHDL

Visit AMIQ at DAC 2010, Booth #1417


AMIQ focuses on adding value to the verification domain through its proprietary tools and over 10 years of expertise in ASIC functional verification and reusable IP development.

Come Learn about the DVT™ IDE

The Design and Verification Tools (DVT) solution is an Eclipse-based integrated development environment (IDE), which enables efficient code writing and simplifies the maintenance of reusable libraries and legacy code. Powerful, yet easy to use, the DVT IDE comprises a complete suite of tools and integrates with all major simulators. It also supports popular verification methodologies like Open Verification Methodology (OVM), Verification Methodology Manual (VMM) and the newly released Universal Verification Methodology (UVM).

The IDE approach offers significant added value over non-IDE editors. A single unified window combines the editor with the syntax checker, linter, class browser, revision control and other useful tools, allowing engineers to navigate easily through a project. The DVT IDE enables fast and smart code development for beginners and experts alike. Designed to maximize verification productivity and quality, the DVT solution is a choice that allows your verification teams to complete their projects faster and increase the likelihood of first tapeout success.

Presentations and Demos

Presentation: The DVT IDE for e and SystemVerilog
10:30-11:00 Monday June 14 at ICDC Stage
Improved code handling can significantly increase the verification productivity and help reach deadlines faster. An overview of the main DVT features will highlight the productivity gains when using an IDE approach to develop new code, as well as to explore and maintain the existing code base.

Presentation: OVM Support in DVT
14:00-14:30 Monday June 14 at OVM World Booth #1350 - Hall B

Demo: VMM Support in DVT
15:00-18:00 Tuesday June 15 at Synopsys Standards Booth #585

Presentation: The DVT IDE for e and SystemVerilog
15:15-15:50 Wednesday June 16 at Exhibitor Forum #1684 - Hall B