<report>
<category name="XVM Architecture">
<check id="XVM.2.2.3" name="UVM.2.2.3" title="Driver Has Analysis Port" status="ERROR" severity="ERROR" autocorrectable="false">
<hit file="/uvm-1.2_ubus/sv/ubus_master_driver.sv" line="28" details="uvm_analysis_port was not found in driver 'ubus_master_driver'" severity="ERROR" />
<hit file="/uvm-1.2_ubus/sv/ubus_slave_driver.sv" line="28" details="uvm_analysis_port was not found in driver 'ubus_slave_driver'" severity="ERROR" />
</check>
<check id="XVM.2.3.8.1" name="UVM.2.3.8.1" title="A monitor shall access interface signals only through the input ports of a 'mon_mp' modport" status="ERROR" severity="ERROR" autocorrectable="false">
<hit file="/uvm-1.2_ubus/sv/ubus_bus_monitor.sv" line="204" details="Illegal direct interface access: 'vif.sig_reset'!" severity="ERROR" />
<hit file="/uvm-1.2_ubus/sv/ubus_bus_monitor.sv" line="209" details="Illegal direct interface access: 'vif.sig_reset'!" severity="ERROR" />
</check>
</category>
<category name="XVM Factory Create">
<check id="XVM.2.1.4.2.6" name="UVM.2.1.4.2.6" title="Class fields (variables) should be constructed using "UVM create calls"" status="ERROR" severity="ERROR" autocorrectable="false">
<hit file="/uvm-1.2_ubus/sv/ubus_bus_monitor.sv" line="174" details="'ubus_transfer' is created using new()" severity="ERROR" />
<hit file="/uvm-1.2_ubus/sv/ubus_slave_monitor.sv" line="106" details="'ubus_transfer' is created using new()" severity="ERROR" />
</check>
<check id="XVM.2.1.4.2.7" name="UVM.2.1.4.2.7" title="For all class fields inside a UVM component, the constructed string name must match the field name" status="ERROR" severity="ERROR" autocorrectable="false">
<hit file="/uvm-1.2_ubus/sv/ubus_bus_monitor.sv" line="174" details="The creation of 'trans_collected' does not use the component's member variable instance name" severity="ERROR" />
<hit file="/uvm-1.2_ubus/sv/ubus_slave_monitor.sv" line="106" details="The creation of 'trans_collected' does not use the component's member variable instance name" severity="ERROR" />
</check>
</category>
</report>
{
"hits": [
{
"categoryName":"XVM Architecture",
"categoryDescription":"''",
"checkName":"UVM.2.2.3",
"checkTitle":"'Driver Has Analysis Port'",
"checkDescription":"'At least one analysis port must be provided in the driver class into which the sequence item should be placed with each item operation.\nThis allows analysis components to connect directly to the driver in case a monitor is unable to fully reconstruct the item.\nExample:\n...\ntask run();\n forever begin\n seq_item_port.get_next_item(item);\n request_analysis_port.write(item);\n ...\n end\nendtask: run'",
"message":"'uvm_analysis_port was not found in driver \'ubus_master_driver\''",
"severity":"ERROR",
"file":"/uvm-1.2_ubus/sv/ubus_master_driver.sv",
"line":28,
"date":"2017-07-24 07:59:41"
},
{
"categoryName":"XVM Architecture",
"categoryDescription":"''",
"checkName":"UVM.2.2.3",
"checkTitle":"'Driver Has Analysis Port'",
"checkDescription":"'At least one analysis port must be provided in the driver class into which the sequence item should be placed with each item operation.\nThis allows analysis components to connect directly to the driver in case a monitor is unable to fully reconstruct the item.\nExample:\n...\ntask run();\n forever begin\n seq_item_port.get_next_item(item);\n request_analysis_port.write(item);\n ...\n end\nendtask: run'",
"message":"'uvm_analysis_port was not found in driver \'ubus_slave_driver\''",
"severity":"ERROR",
"file":"/uvm-1.2_ubus/sv/ubus_slave_driver.sv",
"line":"28",
"date":"2017-07-24 07:59:41"
},
{
"categoryName":"XVM Architecture",
"categoryDescription":"''",
"checkName":"UVM.2.3.8.1",
"checkTitle":"'A monitor shall access interface signals only through the input ports of a \'mon_mp\' modport'",
"checkDescription":"'The \'mon_mp\' port directions should all be configured to input.\n This simulation runtime checks ensure that the monitor will never drive the bus.'",
"message":"'Illegal direct interface access: \'vif.sig_reset\'!'",
"severity":"ERROR",
"file":"/uvm-1.2_ubus/sv/ubus_bus_monitor.sv",
"line":"204",
"date":"2017-07-24 07:59:41"
},
{
"categoryName":"XVM Architecture",
"categoryDescription":"''",
"checkName":"UVM.2.3.8.1",
"checkTitle":"'A monitor shall access interface signals only through the input ports of a \'mon_mp\' modport'",
"checkDescription":"'The \'mon_mp\' port directions should all be configured to input.\n This simulation runtime checks ensure that the monitor will never drive the bus.'",
"message":"'Illegal direct interface access: \'vif.sig_reset\'!'",
"severity":"ERROR",
"file":"/uvm-1.2_ubus/sv/ubus_bus_monitor.sv",
"line":"209",
"date":"2017-07-24 07:59:41"
},