Quick UVM Project Configuration

You can quickly configure your project to use UVM libraries.
Right click on project in Navigator > Properties > Verilog Language > UVM to open the UVM project properties page.

  1. The UVM Project Properties.
  2. Enable/Disable UVM. If you enable UVM for a SystemVerilog project, the UVM library is compiled up-front from the specified location. You can use system variables to specify the location ($UVM_HOME in the snapshot below).
  3. Link Resources. For quick navigation in the library code, you may link (logical link, nothing is created on disk) the library files to your project. This way, although outside your project, the UVM sources will not be shown with gray icons and limited functionality.

Related Reference

Top Files

Working with Linked Resources

UVM Project Properties