August 23rd, 2023

Using Linting to Write Error-Free Testbench Code

This is the story of a team at Siemens that has integrated Verissimo SystemVerilog Linter into their verification process with impressive results. They noticed a significant increase in the quality and reliability of their code. This resulted in reusable, maintainable, and manageable verification IP components. The team used Verissimo to check more than 510 linting rules, reviewing this list regularly and adding new rules as they became available.

July 6th, 2023

AMIQ Celebrating 20 Years in Consulting and EDA

Why did you start AMIQ?
To practice engineering within the semiconductor industry and help customers with high quality services and products
To give something back to the environment that we sprouted from and to prove it is possible to create value with local capital
To work with smart people who have a passion for engineering and to never work for incompetent managers again!

November 22nd, 2022

A Hardware IDE for VS Code Fans

I wondered whether there were any technical reasons to choose one version of DVT IDE over the other. Cristian said that they have worked very hard to make the two implementations as equivalent in functionality as possible. They have a common engine behind both interfaces to ensure consistency in code compilation and analysis. However, there are some differences in the user experience due to the different technologies used by the underlying platforms.

June 29th, 2022

Using an IDE to Accelerate Hardware Language Learning

A discussion with Dr. Srinivas Boppu, Assistant Professor at Indian Institute of Technology (IIT) Bhubaneswar.

March 31st, 2022

AMIQ EDA Adds Support for Visual Studio Code to DVT IDE Family

The product enables engineers to inspect a project through diagrams. Designers can use HDL diagrams such as schematic, state machine, and flow diagrams. Verification engineers can use UML diagrams such as inheritance and collaboration diagrams. Diagrams are hyperlinked and synchronized with the source code and can be saved for documentation purposes.

March 30th, 2022

Ensuring Correctness and Quality of RISC-V Testbenches

Verissimo found many dozens of issues in the testbench code. The Verification Task Group had developed extensive coding guidelines for SystemVerilog and UVM, but they had not previously had an automated way to check them. Unsurprisingly, there were some violations.

February 21st, 2022

Automated Documentation of Space-Borne FPGA Designs

Documentation turned out to be a big challenge. Given that we’re developing a whole new type of application, our design is quite novel, and it evolved a lot over the course of the project as we learned new things and added more functionality. Every time this happened, it was vital that the design documentation be updated correctly to match the design changes. Of course, when a module changes, designers of the adjoining modules need to know.

December 2nd, 2021

Continuous Integration of RISC-V Testbenches

We have fixed many dozens of issues reported by Verissimo. Some were violations of our SystemVerilog/UVM coding guidelines that we previously had no automated way to detect, and some were due to rules we had not considered before. I especially like the rules that warn us about constructs that may work inconsistently on different simulators or that are not even supported on all simulators. It is important for our code to be vendor-neutral and portable.

October 7th, 2021

Delivering Three Key Aspects of IP Quality

There are three main requirements to IP quality. The most obvious is functional correctness, another is IP robustness, and last but not least, IP maintainability. AMIQ EDA has products that help you meet such requirements.

September 13th, 2021

Continuous Integration of UVM Testbenches

The concept is simple: all code changes from all developers are merged back into the main development stream frequently, perhaps as often as every few hours. AMIQ EDA has been running CI checks on the Github repository of the UVM reference implementation for years.