I learned that users of the AMIQ EDA Design and Verification Tools (DVT) IDE family want to have access to all their favorite features even when editing files with preprocessor code. The AMIQ EDA team developed clever heuristics to enable full IDE capabilities when editing such files, just as they do with pure SystemVerilog. These features include navigational hyperlinks, autocomplete, on-the-fly error detection, quick fixes, refactoring, and all the advanced functionality DVT IDE users are addicted to.
For customer support, we’re investing in leveraged assets such as more intuitive user interfaces, more detailed documentation, and demo movies showing how to use our tools. We increased our investment in product quality by growing our QA team and enhancing our regression test suites. On the hiring side, we’ve found that an extensive internship program is a great way to find and train the best engineers.
This is the story of a team at Siemens that has integrated Verissimo SystemVerilog Linter into their verification process with impressive results. They noticed a significant increase in the quality and reliability of their code. This resulted in reusable, maintainable, and manageable verification IP components. The team used Verissimo to check more than 510 linting rules, reviewing this list regularly and adding new rules as they became available.
Why did you start AMIQ?
To practice engineering within the semiconductor industry and help customers with high quality services and products
To give something back to the environment that we sprouted from and to prove it is possible to create value with local capital
To work with smart people who have a passion for engineering and to never work for incompetent managers again!
I wondered whether there were any technical reasons to choose one version of DVT IDE over the other. Cristian said that they have worked very hard to make the two implementations as equivalent in functionality as possible. They have a common engine behind both interfaces to ensure consistency in code compilation and analysis. However, there are some differences in the user experience due to the different technologies used by the underlying platforms.
A discussion with Dr. Srinivas Boppu, Assistant Professor at Indian Institute of Technology (IIT) Bhubaneswar.
The product enables engineers to inspect a project through diagrams. Designers can use HDL diagrams such as schematic, state machine, and flow diagrams. Verification engineers can use UML diagrams such as inheritance and collaboration diagrams. Diagrams are hyperlinked and synchronized with the source code and can be saved for documentation purposes.
Verissimo found many dozens of issues in the testbench code. The Verification Task Group had developed extensive coding guidelines for SystemVerilog and UVM, but they had not previously had an automated way to check them. Unsurprisingly, there were some violations.
Documentation turned out to be a big challenge. Given that we’re developing a whole new type of application, our design is quite novel, and it evolved a lot over the course of the project as we learned new things and added more functionality. Every time this happened, it was vital that the design documentation be updated correctly to match the design changes. Of course, when a module changes, designers of the adjoining modules need to know.
We have fixed many dozens of issues reported by Verissimo. Some were violations of our SystemVerilog/UVM coding guidelines that we previously had no automated way to detect, and some were due to rules we had not considered before. I especially like the rules that warn us about constructs that may work inconsistently on different simulators or that are not even supported on all simulators. It is important for our code to be vendor-neutral and portable.