DVT SystemVerilog IDE User Guide
Rev. 22.1.19, 28 June 2022
Table of Contents
Elaboration is the process that occurs after the code is parsed. From one or more starting points, called tops, all instances have their designs computed, parameters and other constants get their values, generate constructs are instantiated and port connections are established.
In the project build config file, specify the elaboration top(s) with one or more -top [library_name.] top_name directives.
-top work.elem_name - from the specified library, the SystemVerilog module, SystemVerilog configuration, VHDL entity or VHDL configuration is set as the top
-top elem_name - all libraries are searched for the design element and the first found is set as top
-top elem_name:config - the configuration specified is the top, even in the case of a name collision with either a SystemVerilog module or a VHDL entity
If no directive is used, then the elaboration is preceded by a top candidates search through all the designs. A UNSPECIFIED_TOP warning is also displayed in the Console View to mark the absence of any chosen top design.
Note SystemVerilog modules can be instantiated by a VHDL entity and vice versa. You can also specify design tops from either language.