DVT SystemVerilog IDE User Guide
Rev. 22.1.19, 28 June 2022

## 43.14 How to handle Simulator and Command Line Macros

Some simulators define proprietary pre-processing that might have some implications on the actual simulated code (see for example in OVM lib ifdef INCA occurrences).

Also, many times, compilation/run scripts take as arguments macro definitions.

See Build Configurations for enhanced support of simulator commands files.

Until we'll fully integrate with all simulators and/or we provide preferences for specifying macros and means for easily turning them on/off, we recommend to create a dummy *.sv file that you set first in the top files project property as follows:

1. Create a separate dummy *.sv file ( eclipse_simulator_macros.sv) where you'll define simulator macros guarded by ifndefs.

2. Put the dummy macros file in your project.

3. Configure the Project Top Files so that the dummy macros file will be the first one.

4. Rebuild.

Dummy macros might look like: