DVT SystemVerilog IDE User Guide
Rev. 22.1.19, 28 June 2022
To see all instances of a module, interface or program, hover on the name with the mouse cursor while holding down the Ctrl key and select Show Instances.
You can also place the editor cursor on it's name then right click and select Show > Instances.
The results are presented in the Search View.
Tip: You can also trigger this functionality from a view's context menu, for example from the Types View.
Note: If a top is specified using -top directive in build configuration file, it is displayed in the Show Instances action label. After elaboration an instance can be resolved to a design element different from the one specified in its declaration.
Note: This functionality works in mixed-language designs, for example when you have a VHDL entity instantiated in a Verilog module or a Verilog module instantiated in a VHDL component.