DVT SystemVerilog IDE User Guide
Rev. 24.1.5, 13 March 2024

5.3 Synthesis Checks

ID Message
SIGNAL_MULTIPLE_DRIVERSSignal # has multiple drivers
ILLEGAL_VARIABLE_ASSIGNMENTSVariable # written by both continuous and procedural assignments
ILLEGAL_VARIABLE_ASSIGNMENTSVariable # written by more than one continuous assignment
SENSITIVITY_MISSINGMissing # from sensitivity list
SENSITIVITY_MIXED_CONTROLMixed edge/non-edge controls in sensitivity list may not be synthesizable
ASSIGNMENT_BLOCKINGBlocking assignment of # in sequential logic (use non-blocking assignment)
WIDTH_MISMATCH_PADDINGAssignment to #-bit value from #-bit value
WIDTH_MISMATCH_PADDINGReturning # of #-bit type for function of #-bit return type
WIDTH_MISMATCH_PADDINGAssignment to array element of #-bit type from # of #-bit type
WIDTH_MISMATCH_ROUNDINGAssignment to #-bit value from #-bit value
WIDTH_MISMATCH_ROUNDINGReturning # of #-bit type for function of #-bit return type
WIDTH_MISMATCH_ROUNDINGAssignment to array element of #-bit type from # of #-bit type
WIDTH_MISMATCH_TRUNCATIONAssignment to #-bit value from #-bit value
WIDTH_MISMATCH_TRUNCATIONReturning # of #-bit type for function of #-bit return type
WIDTH_MISMATCH_TRUNCATIONAssignment to array element of #-bit type from # of #-bit type
WIDTH_MISMATCH_TRUNCATIONInteger literal # will be truncated to fit on # bits
WIDTH_MISMATCH_IMPLICIT_SIGNALAssignment to # of #-bit type from # of #-bit type
INTEGER_SIGN_OVERFLOWInteger literal # on 32 bits has sign overflow
UNDRIVEN_INPUT_PORTInput port # is not driven
PORT_CONNECTIONCannot drive input port #
PORT_CONNECTIONOutput port # of module # connected to input port # of module #
PORT_CONNECTIONOutput port # of module # connected to # of reg data type"
PORT_CONNECTIONInout port # of module # connected to variable #
SIGNAL_NOT_RESETSignal # is not reset
MULTIPLE_CLOCKS_BLOCKProcedural block driven by multiple clocks (#)
MULTIPLE_RESETS_BLOCKProcedural block driven by multiple resets (#)
MULTI_BIT_EDGE_CONTROLMulti-bit signal # used as edge control
OUTPUT_PORT_READReading from an output port # is not recommended
FEEDTHROUGH_DETECTEDFeedthrough from # to #
INTERNAL_GENERATED_CLOCKClock signal # is not an input port
INTERNAL_GENERATED_RESETReset signal # is not an input port
IMPLICIT_DECLARATIONImplicit declaration of # using `default_nettype set to #