DVT SystemVerilog IDE User Guide
Rev. 22.1.19, 28 June 2022

41.6.1 Top candidates

When no top design element is specified in the project build config file, then any design element that satisfies the following requirements is considered a top:

  1. The design element is either a SystemVerilog module, a SystemVerilog program, a VHDL entity or a VHDL configuration. Do note that a SystemVerilog configuration cannot be a candidate.

  2. The design element is not instantiated anywhere. Even instantiations under inactive generate constructs are considered and rule out the element in question.

  3. Customizable: The design element has sub-instances or local generate constructs. This requirement can be disabled by specifying in the project build config the following directive: +dvt_enable_elaboration_empty_tops+true.

As mentioned before, a mixed-language project can have any combination of SystemVerilog, SystemVerilog or VHDL top candidates.