21.3.3 Component Diagram Actions

DVT IDE for VS Code SystemVerilog User Guide

Rev. 23.1.12, 23 May 2023

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Installation
- System Requirements
- Install DVT for VS Code from Marketplace
- Install DVT for VS Code from VSIX
- Install DVT for VS Code Using a Pre-Packed Distribution
- Set the License
Predefined Projects
Build Configurations
- Project Natures
- Non-top files
- default.build
- Auto-config
- Simulator Log-config
- Emulating compiler invocations
- Multiple .build Files
- Compatibility Modes
- Paths
- Strings
- Comments
- Environment Variables
- Including Other Argument Files
- All Build Directives
- SystemVerilog OVM or UVM Library Compilation
- Xilinx Libraries Compilation
- Intel(Altera) Quartus Libraries Compilation
- Questa Libraries Compilation
- Use of External Programs
Compile Checks
- Compile Waivers
- Semantic Checks
- Synthesis Checks
- Performance Checks
- Dead Code Checks
- Non Standard Checks
Quick Fix Proposals
Content Assist (Autocomplete)
- Content Assist for CamelCase and Underscore
- Code Templates
- Module Automatic Instantiation
- Override Functions Using Autocomplete
- Implement Extern Functions Using Autocomplete
- Generate Setters and Getters Using Autocomplete
- Use Assignment Pattern for Struct Type Variable
Hyperlinks
Show Usages
Show Readers or Writers
Show Call Hierarchy
Show Type Hierarchy
Show Constraints
Show Instances
Peek Exploration
Refactoring
Override Functions
- Override Annotation
- Override Using Command Palette
- Override Using Autocomplete
Generate Setters and Getters
Code Factory
Code Formatting
- Whitespace
- Indentation
- Vertical Alignment
- Line Wrapping
- Disable Format for Code Sections
Breadcrumb Navigation Bar
- Design Breadcrumb
- Verification Breadcrumb
- Scope Breadcrumb
> Diagrams
- UML Diagrams
- Design Diagrams
- > UVM Components Diagrams
- WaveDrom Timing Diagrams
- Bit Field Diagrams
  - Bit Field Diagrams for UVM registers
  - Bit Field Diagrams for packed data types
- Common Diagram Actions
- Common Diagram Toolbar
Syntax Coloring
Tooltips
- Comments Formatting
  - Javadoc
  - Natural Docs
Workspace Symbols
Views
- Problems View
- Outline View
- Compiled Files View
- Compile Order View
- Design Hierarchy View
- Verification Hierarchy View
- Diagnostics View
Quick Search in Views
- CamelCase
- Simple Regex
- Hierarchical Search
- Search for Members
- Search Port in Design Hierarchy
- Search Port in Verification Hierarchy
Content Filters
- Content Filters XML Syntax
- Filtering by Element Type
- Content Filters Examples
- Predefined Content Filters
Macros Support
- Inactive Code Highlight
- Macro Expansion
External Tools Integration
UVM Support
- Show UVM Sequence Tree
Scripts
- dvt_code.sh
  - dvt_code.sh Syntax
  - dvt_code.sh Examples
- dvt_ls.sh
  - dvt_ls.sh Syntax
  - dvt_ls.sh Examples
Custom Scripts
SCM Checkout Hook
Application Notes
- Flow Integration
- Environment Variables
- Design Elaboration
- Compilation Speed-up
- Encrypted VIP Support
- FPGA Support
  - Intel(Altera) Quartus
    - Intel(Altera) Quartus Libraries Compilation
  - Xilinx ISE/Vivado
    - Xilinx Libraries Compilation
Handy VS Code Documentation Pointers
What is New?
How to Report an Issue?
Legal Notices
Third Party Licenses
Q & A
- Can I deactivate DVT support for a workspace even though one of my workspace folders contains a .dvt directory?

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21.3.3 Component Diagram Actions

The following operations are available in the context menu:

"Go to Create Call" Jump to the create call for the selected instance.
"Go to Type" Jump to the declaration of the selected element's type. It is available for nodes and labeled edges.

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