The Design Hierarchy View presents recursively the instances in a Verilog module or the instances in a VHDL entity or component implementation. Cross-language design hierarchies are also supported.

To open the Design Hierarchy View use the DVT: Focus on Design Hierarchy View command.

You cand also position the editor cursor on the name of a design element and use the command DVT: Show Design Hierarchy. The Design Hierarchy View opens with the chosen element set as the top of the hierarchy.

By using the DVT: Select Design Hierarchy Top command a quick pick will appear to select from top modules for Verilog or top architectures for VHDL. For Verilog, a top element is a module that instantiates other design elements and it is not itself instantiated. Similar for VHDL top architectures.

The view label shows the current project, the current top component.

You can scroll through the tree of instances using:

By clicking on a design element it shows the ports of the selected element. You can double-click on an instance to go to its declaration. Double-click on a port to go to where it is connected.

Right-click on an instance or on a port in the hierarchy and you have the following options :

You can use the filters to locate a specific instance or port. More details here.