During elaboration, parameters (or generics in VHDL) get their values computed. The following sources, ordered by importance, are searched: 1.
Configuration overrides. Any override of a parameter in a SystemVerilog config or a VHDL configuration rule is considered first.
// SystemVerilog config cfg; instance top.inst use amod #(.PARAM(1)) endconfig -- VHDL configuration cfg of top_entity for rtl for inst : aent use entity work.aent
generic map (PARAM => 1);
end for; end for; end configuration; 2.
Defparam assignments
// SystemVerilog defparam top.inst.PARAM = 1; 3.
Instantiation overrides
// SystemVerilog amod #(.PARAM(1)) inst(); -- VHDL inst : entity work.aent
generic map (PARAM => 1); 4.
Default values
// SystemVerilog parameter int PARAM = 1; -- VHDL generic (PARAM : integer := 1); |