DVT IDE for VS Code SystemVerilog User Guide
Rev. 24.1.8, 24 April 2024
- Installation
- User Interface
- Predefined Projects
- Build Configurations
- Project Natures
- Non-top files
- default.build
- Auto-config
- Simulator Log-config
- Emulating compiler invocations
- Multiple .build Files
- Compatibility Modes
- Paths
- Strings
- Comments
- Environment Variables
- Including Other Argument Files
- Build Persistence
- All Build Directives
- SystemVerilog OVM or UVM Library Compilation
- Xilinx Libraries Compilation
- Intel(Altera) Quartus Libraries Compilation
- Questa Libraries Compilation
- Use of External Programs
- Compile Checks
- Quick Fix Proposals
- Content Assist (Autocomplete)
- Hyperlinks
- Show Usages
- Show Readers or Writers
- Show Call Hierarchy
- Show Type Hierarchy
- Show Constraints
- Show Instances
- Peek Exploration
- Refactoring
- Override Functions
- Generate Setters and Getters
- Code Factory
- Code Formatting
- Breadcrumb Navigation Bar
- > Diagrams
- Syntax Coloring
- Tooltips
- Workspace Symbols
- Views
- Quick Search in Views
- Content Filters
- Macros Support
- Inactive Generates Code Highlight
- Database Out of Sync Notification
- External Tools Integration
- UVM Support
- Scripts
- Custom Scripts
- SCM Checkout Hook
- Memory Monitor
- Application Notes
- Handy VS Code Documentation Pointers
- What is New?
- How to Report an Issue?
- Legal Notices
- Third Party Licenses
- Q & A
Table of Contents
UVM Components Diagrams help you inspect and document the structure of a verification environment.
You can create a component diagram in one of the following ways:
Right-click in the Verification Hierarchy View and select "Show Diagram". This way is faster, but the generated diagram might not be completely accurate because it's missing the runtime information.
Generate the diagram using the simulator and open it in DVT. This way requires to run the simulation with some additional files compiled, but the generated diagram will be complete.
