Verissimo SystemVerilog Testbench Linter User Guide
Rev. 18.1.29, 13 September 2018

4.3.1 Default DVT Compatibility Mode

The +dvt_init+dvt directive resets the builder to the dvt default state.

File Extension to Language Syntax Mapping

Syntax Extensions
Verilog 2001.v, .vh
System Verilog 1800-2012.vp, .vs, .vsh, .v95, .v95p, .sv, .svh, .svp, .svi, .sva
VHDL 1076-2008.vhd, .vhdl
e Language 1647-2011.e
PSS DSL.pss
C/C++.c, .h, .cpp, .cc, .cxx
Shared objects (C/C++ libraries).so, .a, .o

Language Syntax for Unmapped Extensions: Skip unmapped extensions.

Language Syntax for Included Files: Included files are parsed as specified by the extension mapping.

Mode Specific Directives

Directive Description
+dvt_ext_map+<syntax>+<ext>Files with <ext> extension are parsed using the specified <syntax>. See the list below for more details regarding <syntax>.
+dvt_ext_unmap+<ext>Files with <ext> extension are parsed using the Language Syntax for Unmapped Extensions.
+dvt_ext_unmapped_syntax+<syntax>Set the Language Syntax for Unmapped Extensions. See the list below for more details regarding <syntax>.
+dvt_ext_unmap_allAll files are parsed using the Language Syntax for Unmapped Extensions.
+dvt_ext_included+by_ext


+dvt_ext_included+by_parent
by_ext: The included files are parsed using the syntax as specified by directives, that is using by ext syntax (if explicit) or the syntax for unmapped extensions


by_parent: Included files are parsed using the syntax that was used for parsing the including file

Specifying a <syntax>

To specify the <syntax> for the directives above, one should use any of the following strings, case-insensitive:

1364-1995, Verilog_95

1364-2001-noconfig, Verilog_2001_noconfig

1364-2001, Verilog_2001

1364-2005, Verilog_2005

VAMS-2.3, Verilog_AMS_23

1800-2005, SystemVerilog_2005

1800-2009, SystemVerilog_2009

1800-2012, SystemVerilog_2012, SystemVerilog

1647-2011, e_2011, e

1076-1987, VHDL_87

1076-1993, VHDL_93

1076.1-1999, VHDL_AMS_99

1076-2000, VHDL_2000

1076-2002, VHDL_2002

1076.1-2007, VHDL_AMS_2007

1076-2008, VHDL_2008, VHDL

PSS

SKIP

The dot (.) for specifying <ext> is optional. For example +dvt_ext_map+verilog_1364_1995+.svh and +dvt_ext_map+verilog_1364_1995+svh are equivalent.

You can specify more extensions at once, for example +dvt_ext_map+verilog_1364_1995+.svh+svp.

When several directives change the syntax of a specific <ext>, the last one wins.

Examples

  • I want to parse .c and .v files as SystemVerilog:

+dvt_init+dvt // By default .c are skipped and .v are parsed with Verilog 2001 syntax
+dvt_ext_map+SystemVerilog_2012+.v+.c // Now .c and .v are parsed with SystemVerilog 2012

Note Every time you re-map an already mapped extension, DVT will warn you. For the example above, you get the following warnings:

.v was previously mapped to Verilog_2001
.c was previously mapped to Skip

  • I want the .vp files to be parsed with the Language Syntax for Unmapped Extensions:

+dvt_init+dvt // By default .vp is parsed with SystemVerilog 2012.
+dvt_ext_unmap+.vp // Because by default the unmapped extensions are skipped, .vp files will be skipped

  • I want to change the Language Syntax for Unmapped Extensions:

+dvt_init+dvt // By default the unmapped extensions are skipped
+dvt_ext_unmapped_syntax+Verilog_95 // Now unmapped extensions, for example .foo, will be parsed as Verilog 95

  • I want to configure everything from scratch:

+dvt_init+dvt
+dvt_ext_unmap_all // All files are skipped
+dvt_ext_unmapped_syntax+Verilog_95 // Compile all files with unmapped extensions as Verilog 95
+dvt_ext_map+skip+.cpp // Skip .cpp files
+dvt_ext_map+SystemVerilog_95+.sv // Compile .sv as SystemVerilog
+dvt_ext_map+VHDL_1076_1_1999+.vhd // Compile .vhd as VHDL-AMS

  • I want to parse everything as SystemVerilog

+dvt_init+dvt
+dvt_ext_unmap_all // All files are skipped
+dvt_ext_unmapped_syntax+SystemVerilog  // All files are parsed as SystemVerilog