DVT IDE for VS Code VHDL User Guide
Rev. 24.1.7, 9 April 2024
- Installation
- User Interface
- Predefined Projects
- Build Configurations
- Project Natures
- Non-top files
- default.build
- Auto-config
- Simulator Log-config
- Emulating compiler invocations
- Multiple .build Files
- Compatibility Modes
- Paths
- Strings
- Comments
- Environment Variables
- Including Other Argument Files
- Build Persistence
- All Build Directives
- SystemVerilog OVM or UVM Library Compilation
- Xilinx Libraries Compilation
- Intel(Altera) Quartus Libraries Compilation
- Questa Libraries Compilation
- Use of External Programs
- Compile Checks
- Quick Fix Proposals
- Content Assist (Autocomplete)
- Hyperlinks
- Show Usages
- Show Readers or Writers
- Show Instances
- Peek Exploration
- Refactoring
- Code Factory
- Code Formatting
- Breadcrumb Navigation Bar
- > Diagrams
- Syntax Coloring
- Inactive Generates Code Highlight
- Database Out of Sync Notification
- Tooltips
- Workspace Symbols
- Views
- Quick Search in Views
- Content Filters
- External Tools Integration
- Scripts
- Custom Scripts
- SCM Checkout Hook
- Memory Monitor
- Application Notes
- Handy VS Code Documentation Pointers
- What is New?
- How to Report an Issue?
- Legal Notices
- Third Party Licenses
- Q & A
Table of Contents
Design Diagrams help you inspect and document the structure of a design element.
To create a design diagram, place the cursor over a type, instance, or state variable in the editor, use the "DVT: Show Diagram" command and choose the type of diagram you are interested in.
The Design Breadcrumb is updated with the diagram's input when the diagrams gets generated.
