The key enhancements and new capabilities that DVT version 3.5 brings to its users include:
- Enhanced compilation for SystemVerilog and VHDL
- Improved UVM Support
- Redesigned tool configuration and preference sharing capabilities
- Streamlined GUI experience
Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.
Amiq DVT Eclipse IDE provides IDE for design and verification languages like "e", System Verilog, VHDL. Visual C like stuff. Capacity. "Took one customer's 15 M lines of code, no problem."
DVT is used by Cadence for training classes on Udacity. Don't forget we provide free licenses for academic use!
DVCon 2013 Cadence Verification Alliance Interview: "Support for mixed design and verification languages"
Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie. Discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.
Now, regardless of what language(s) your design/testbench was written in, you can use one environment to navigate seamlessly through large projects, easily see the big picture, and understand the whole design.
This cross-language integration does not mean translation from a language to another, but easy navigation through the source code, no matter in what language is written, using DVT's advanced navigation capabilities and unified perspective GUI. Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.