Events

March, 2014

DVCon 2014 Panel: Did We Create the Verification Gap?

The gap is more a matter of attitude. "Until recently, verification has been a second-class citizen in comparison to design." notes Cristian Amitroaie, CEO of AMIQ.

March, 2014

AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE

The key enhancements and new capabilities that DVT version 3.5 brings to its users include:

  • Enhanced compilation for SystemVerilog and VHDL
  • Improved UVM Support
  • Redesigned tool configuration and preference sharing capabilities
  • Streamlined GUI experience
June, 2013

John Cooley - My Cheesy Must See List for DAC 2013

Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.
Amiq DVT Eclipse IDE provides IDE for design and verification languages like "e", System Verilog, VHDL. Visual C like stuff. Capacity. "Took one customer's 15 M lines of code, no problem."

March, 2013

What is that cool coding environment?

DVT is used by Cadence for training classes on Udacity. Don't forget we provide free licenses for academic use!

February, 2013
February, 2013

DVCon 2013 Cadence Verification Alliance Interview: "Support for mixed design and verification languages"

Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie. Discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.