AMIQ EDA Launches Specador Documentation Generator for e Language, SystemVerilog, Verilog, and VHDL Projects
Specador uses dedicated language parsers for e, SystemVerilog, Verilog, and VHDL to help design and verification engineers generate and maintain well-organized documentation with minimum effort.
The gap is more a matter of attitude. "Until recently, verification has been a second-class citizen in comparison to design." notes Cristian Amitroaie, CEO of AMIQ.
The key enhancements and new capabilities that DVT version 3.5 brings to its users include:
- Enhanced compilation for SystemVerilog and VHDL
- Improved UVM Support
- Redesigned tool configuration and preference sharing capabilities
- Streamlined GUI experience
Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.
Amiq DVT Eclipse IDE provides IDE for design and verification languages like "e", System Verilog, VHDL. Visual C like stuff. Capacity. "Took one customer's 15 M lines of code, no problem."
DVT is used by Cadence for training classes on Udacity. Don't forget we provide free licenses for academic use!