|March, 2016||DVCon 2016 EDACafe Interview: "New features in DVT Eclipse IDE: schematics, trace diagrams, quick fixes and more."|
|March, 2016||Exhibitor at DVCon 2016
AMIQ EDA Unveils New Verilog and VHDL Design-Oriented Diagrams
AMIQ EDA unveils new Verilog and VHDL design-oriented diagrams that enable both design and verification engineers to easily visualize, explore, and understand RTL code.
|January, 2016||A Discussion About Source Code Copy-Paste: Is it good or bad? Preventing or detecting?
At a recent EDA event, Semi-IP Systems talked with Cristian Amitroaie, the CEO of AMIQ, about the good and bad side of developing software from code that is copied from another program.
John Cooley - My Cheesy Must See List for DAC 2015
Amiq DVT Debugger Add-On is an add-on to VCS/Questa/Incisive to let an engineer NOT have to continuously switch between his editor and the "e"/SystemVerilog/VHDL simulator
|June, 2015||Exhibitor at DAC 2015|
AMIQ EDA Introduces Duplicate Code Detection in Its Verissimo SystemVerilog Testbench Linter
AMIQ EDA announces new rules for duplicate code detection in its Verissimo SystemVerilog Testbench Linter to help design and verification engineers improve code quality and reduce maintenance costs.
|March, 2015||DVCon 2015 EDACafe Interview: "How the new debugger integration in combination with the powerful code navigation and inspection features of the DVT IDE, eliminates the need to switch continuously between a code editor and simulator and enable users to debug their code more efficiently."|
|March, 2015||Exhibitor at DVCon 2015
AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL
AMIQ EDA announced the release of the DVT Debugger Add-On Module for
the e language, SystemVerilog, Verilog, and VHDL, an extension to the DVT
IDE that allows design and verification engineers perform debugging from the
same place where they develop their code, in order to simplify and speed up
|October, 2014||Exhibitor at DVCon Europe 2014
AMIQ EDA Introduces New Capabilities in Its Verissimo SystemVerilog Testbench Linter
AMIQ EDA announced the release of new capabilities for dead code analysis and improved reporting of Pass/Fail checks in its
Verissimo SystemVerilog Testbench Linter - a static code analysis tool for the SystemVerilog language and Universal Verification Methodology (UVM).
The newly introduced capabilities enable engineers to further improve code performance and testbench reliability and reduce maintenance costs.
|June, 2014||DAC 2014 ChipDesign Interview: Why Don't Software Programmers like Comments?|
John Cooley - My Cheesy Must See List for DAC 2014
Their new Specador automatically generates HTML documentation.
|June, 2014||Exhibitor at DAC 2014|
AMIQ EDA Launches Specador Documentation Generator for e Language, SystemVerilog, Verilog, and VHDL Projects
Specador uses dedicated language parsers for e, SystemVerilog, Verilog, and VHDL to help design and verification engineers generate and maintain well-organized documentation with minimum effort.
|March, 2014||Exhibitor at SNUG San Jose - Designer Community Expo|
|March, 2014||DVCon 2014 Panel: Did We Create the Verification Gap?
The gap is more a matter of attitude. "Until recently, verification has been a second-class citizen in comparison to design." notes Cristian Amitroaie, CEO of AMIQ.
|March, 2014||DVCon 2014 EDACafe Interview: "About AMIQ, IDEs and what's new in DVT Eclipse IDE version 3.5"|
|March, 2014||Exhibitor at DVCon 2014
AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE
The key enhancements and new capabilities that DVT version 3.5 brings to its users include:
|June, 2013||DAC 2013 ChipDesign Interview: Code Integration Facilitates Chip Innovation|
John Cooley - My Cheesy Must See List for DAC 2013
Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.
|June, 2013||Exhibitor at DAC 2013|
|March, 2013||What is that cool coding environment?
DVT is used by Cadence for training classes on Udacity. Don't forget we provide free licenses for academic use!
|March, 2013||Exhibitor at CDNLive! San Jose|
|Feb, 2013||DVCon 2013 Cadence Verification Alliance Interview: "Support for mixed design and verification languages"
Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie. Discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.
|Feb, 2013||Exhibitor at DVCon 2013
AMIQ CEO explains how DVT editor supports e, SystemVerilog, Verilog, VHDL
Now, regardless of what language(s) your design/testbench was written in,
you can use one environment to navigate seamlessly through large projects,
easily see the big picture, and understand the whole design.
AMIQ EDA Announces Cross-Language Capabilities for Mixed-Language Projects
"Previous versions of the DVT IDE allowed users to work on projects that contained source code written in multiple languages,
such as e, SystemVerilog, Verilog, and VHDL. However, some of the IDE’s specific editing and navigation features were restricted
to the scope of a single language. Our goal has been to improve the cross-language integration and will continue to focus on this topic,
in order to support the design and verification teams that have new or legacy code written in multiple languages, to increase their productivity."
|June, 2012||Video: DAC 2012 Update on AMIQ's DVT IDE - New RTL Design Work Flow Support
"Readers of this blog and of Team Specman will recall that Integrated Development Environment (IDE) and
verification services provider AMIQ has been in the vanguard of supporting functional verification
methodologies and testbench creation for years. The success of verification engineers using AMIQ's
"DVT" IDE product has been increasingly noticed by their RTL designer colleagues such that AMIQ is
now adding new capabilities to DVT to support RTL design work flows."
John Cooley - My Cheesy Must See List for DAC 2012
Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.
|June, 2012||Exhibitor at DAC 2012|
AMIQ Releases New Design-Oriented Features in the DVT IDE
"The Design and Verification Tools IDE has been created from the beginning, as its name shows,
with both design and verification in mind. Although DVT's early adopters were verification engineers,
its popularity has rapidly increased among design engineers. The capabilities released today are the
result of listening to the designers' feedback and requests.
These features enable design engineers to easily understand how a signal propagates in a design,
connect two modules across the design hierarchy, and inspect and document a module structure.",
|May, 2012||Exhibitor at 'ChipEx' Israel|
|May, 2012||AMQ Has a New Logo
"The AMIQ team is friendly, creative, and has a passion for bringing sharp ideas to life.
These qualities are reflected by the new shape of the logo as well as by its dark blue color.
The dark blue also captures AMIQ's focus on deep knowledge and domain expertise, excellence, integrity,
and commitment to the customers worldwide. The red color echoes the two companies' dynamism and passion,
qualities that have been passed on by the three founders since inception.",
|March, 2012||Exhibitor at SNUG San Jose - Designer Community Expo|
|March, 2012||Presenter at CDNLive! San Jose: "Design and Testbench Analysis: The SystemVerilog Challenge "|
|March, 2012||DVCon 2012 EDACafe Interview: "Verissimo SystemVerilog Testbench Linter "|
|March, 2012||DVCon 2012 Cadence Verification Alliance Interview: "Verissimo SystemVerilog Testbench Linter "
"At DVCon 2012, long time Cadence Connections Partner AMIQ launch new product -- the "Verissimo" SystemVerilog testbench linter is optimized for functional verification with UVM, and supports users adding their own custom rules. In this video AMIQ's CEO Cristian Amitroaie reviews the highlights of this exciting new offering."
|March, 2012||Exhibitor at DVCon 2012|
|February, 2011||Effective Audit of Testbenches with AMIQ's Verissimo SystemVerilog Testbench Linter
"The Verissimo SystemVerilog Testbench Linter is a a coding guideline and verification methodology compliance checker
that enables engineers to perform an effective audit of their testbenches and helps them meet the requirements of today's
complex functional verification.",
|Feb, 2012||Exhibitor at SemIsrael Verification Day|
|October, 2011||Users rate 29 more tools shown at DAC'11
It was the odd side niche tools like Amiq DVT Eclipse, Atrenta Spyglass, Duolog Bitwise, that caught user's mindshare in the Verilog/VHDL simulation space.
|June, 2011||Exhibitor at DAC 2011|
|May, 2011||Exhibitor at 'ChipEx' Israel|
|May, 2011||Exhibitor at CDNLive!|
|May, 2011||New Advanced e Language Debugging Capability in DVT to Boost Verification Productivity
"The DVT e-Debug feature integrates seamlessly with Cadence® Incisive® Enterprise Simulator
to provide further productivity and quality increase in the verification process.",
|April, 2011||Exhibitor at SNUG San Jose - Designer Community Expo|
|March, 2011||DVCon 2011 EDACafe Interview: "OVM 2 UVM Migration "|
|March, 2011||DVCon 2011 Cadence Verification Alliance Interview: "AMIQ’s DVT IDE and UVM 1.0"|
|March, 2011||Exhibitor at SemIsrael Verification Day|
|March, 2011||Exhibitor at DVCon 2011|
|January, 2011||Exhibitor at EDSFair Japan|
DVT is aimed at newcomers and experts working on system design and verification.
Based on the Eclipse open source platform, DVT is aimed at newcomers and experts working on system design and verification. "I had experience of IDEs in the software development world," Cristian Amitroaie explained. "We urgently needed one in our consulting business and would have bought one if it existed!". Instead, Amiq developed its own IDE and, when customers saw the productivity gains in verification, they wanted it too.
|October, 2010||Exhibitor at CDNLive! San Jose|
|October, 2010||Exhibitor at CDNLive! Israel|
|October, 2010||AMIQ Releases the Automated UVM Compliance-Checking Capability
"The complexity of SoC Verification faced by customers today requires more stringent adherence
to the UVM reuse verification methodology in order to ensure more seamless IP integration. Capabilities like
AMIQ's DVT UVM Compliance Checker are essential for customers to check that their verification IP is consistent
with the UVM in order to accelerate time to SoC and silicon realization.", said Michael Stellfox.
|October, 2010||Exhibitor at SAME 2010, Sophia Antipolis, France|
|September, 2010||Exhibitor at Cadence "Technology on Tour" Roadshow 2010, Sweden|
|July, 2010||Exhibitor at CDNLive! Tokyo|
|June, 2010||Exhibitor at DAC 2010|
|June, 2010||BigBand Networks Adopts AMIQ's DVT to Shorten Its Verification Schedules
"AMIQ's eDT makes our verification engineers more efficient. The advanced search features, hyperlinks, and class browser
are great enhancements to functional verification, which help us to increase the quality of our projects", said Tamir Ostfeld,
Sr. Director of VLSI Development at BigBand Networks.
|June, 2010||AMIQ Announces the Release of the OVM to UVM Migration Wizard
With the OVM to UVM Migration Wizard capability, the DVT provides automatic OVM to UVM migration,
which helps users that adopt UVM to get up to speed in record time.
|June, 2010||AMIQ Outsources Its DVT Sales Activities in Asia and Israel to EDAcon Partners
"AMIQ's DVT platform makes a significant impact on the efficiency and quality of verification code development and maintenance",
said Coby Hanoch, EDAcon Partners' President and CEO.
"We are impressed with how fast the verification engineers see the value of this solution and adopt it".
|May, 2010||UVM Support
Starting with the 2.9.3 release, the DVT IDE provides support for both UVM-based code development and OVM to UVM migration.
|May, 2010||Exhibitor at 'ChipEx' Israel|
|May, 2010||Exhibitor at CDNLive! Munich|
|March, 2010||Exhibitor at SNUG San Jose - Designer Community Expo|
|February, 2010||DVCon 2010 EDACafe Interview: "Development Environment for e & SystemVerilog"|
|February, 2010||DVCon 2010 Cadence Verification Alliance Interview: "AMIQ and DVT"|
|February, 2010||Exhibitor at DVCon 2010|
|September, 2009||Press Release: DVT Provides OVM Compliance Review Capabilities
AMIQ today announced the availability of compliance-checking rules for the Open Verification Methodology (OVM)
in the DVT integrated development environment (IDE).
|September, 2009||Exhibitor at CDNLive! Israel|
|July, 2009||Exhibitor at DAC 2009|
|July, 2009||Exhibitor at Synopsys DAC Interoperability Breakfast|
|May, 2009||Exhibitor at CDNLive! Munich|
|May, 2009||Team Specman Blog: "e Coding Made Easy with the DVT Integrated Development Environment"|
|April, 2009||Correct Designs showcase DVT at Door64 as a tool that is best used to run the lab-exercises included with their SystemVerilog training classes.|
|November, 2008||Exhibitor at CDNLive! Israel|
|June, 2008||Reached 1000 Users Milestone|
|June, 2008||DAC 2008 EDACafe Interview: "AMIQ and DVT"|
|June, 2008||Exhibitor at DAC 2008|
|May, 2008||SCDsource: IEEE 'e' language update shows continuing momentum
Binyamini pointed to third-party support for "e" language verification. AMIQ offer native "e" language support inside tools. AMIQ offers an Eclipse-based development environment for "e" and SystemVerilog.
|April, 2008||Exhibitor at CDNLive! Munich|
|February, 2008||First Commercial Release|
|November, 2006||DVT Forum|
|October, 2006||Presentation at 'Club T' Cadence Verification User's Group - Bristol and Munich|
|April, 2006||EE Times: IEEE standardizes 'e' language
AMIQ Consulting (Bucharest, Romania) last month also rolled out an IDE for the "e" language based on the Eclipse open-source standard. The company has already seen a lot of demand, said founder Cristian Amitroaie. AMIQ also offers an "e" language parser, import viewer and name checker. "For AMIQ, the final step in the IEEE standardization process is a further confirmation that Cadence is committed to go all the way and support the 'e' language technology," Amitroaie said. read more >>
|March, 2006||First Release|
|November, 2005||EE Times: SystemVerilog won't kill 'e', say proponents
AMIQ Consulting (Bucharest, Romania) offers EParser, an "e" language parser that EDA vendors or in-house design groups can use to build "e" language tools. Cristian Amitroaie, AMIQ Consulting's founder, noted that IEEE standardization will make the language open, prove it to be mature and increase customer confidence in what is no longer a "proprietary" language.
|November, 2005||Cadence: Initial Ballot to Make e Language an IEEE Standard Passes Overwhelmingly
"The standardization of e is an important milestone for us," said Cristian Amitroaie, founder of AMIQ Consulting. "We are the first provider of an e parser, in addition to services and tools for the e language. Stability and recognition afforded by the IEEE standardization acts as a catalyst to broaden our market opportunities. We invested in the e parser to speed-up the development of e-related design automation tools in the context of an established standard. We expect this investment to show its value." read more >>
|2004||Donate first eParser to IEEE1647|