AMIQ EDA Launches Specador Documentation Generator for e Language, SystemVerilog, Verilog, and VHDL Projects

June 2, 2014, San Francisco, CA — AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today announced the launch of Specador Documentation Generator, a tool that automatically generates accurate HTML documentation from the source code.

Specador uses dedicated language parsers for e, SystemVerilog, Verilog, and VHDL to help design and verification engineers generate and maintain well-organized documentation with minimum effort. It is especially useful for packaging IPs, either for the IP providers or for those implementing an IP-oriented flow in their company.

The documentation generated with Specador is always in sync with the source code, thus eliminating meticulous and problematic tasks like maintaining diagrams and updating lists of ports or functions to reflect the current revision number. As such, Specador saves, engineers' time and reduces maintenance costs.

"Integrating Specador into existing development flows is straightforward and the documentation can be extracted immediately", said Cristian Amitroaie, CEO of AMIQ. "By converting source code comments into effective documentation, Specador encourages one of the too often neglected best programming practices: commenting your code. But even if the code is poorly commented, Specador generates useful cross-linked structured documentation including class and design hierarchies and diagrams."

AMIQ EDA is exhibiting at DAC, Booth 1214, on June 2 - 4, 2014, in San Francisco and besides Specador, it is showcasing its products DVT Eclipse IDE and Verissimo SystemVerilog Testbench Linter.


AMIQ EDA focuses on adding value to the design and verification domains through its proprietary code development and analysis tools. Since 2006, its core solution - Design and Verification Tools (DVT) - the first IDE for the e language, SystemVerilog, and VHDL, has helped engineers increase the speed and quality of code development and simplify debugging, enabling them to complete their projects faster. Verissimo SystemVerilog Testbench Linter has been used by verification groups to improve testbench code reliability as well as implement best coding practices and their own specific guidelines. For more information about AMIQ EDA and its solutions, visit and

Press Contact

Cristian Amitroaie