DVT e Language IDE User Guide
Rev. 20.1.5, 27 March 2020
Table of Contents
UVM Components Diagrams help you inspect and document the structure of a verification environment.
To generate the diagram, Right-click in the Verification Hierarchy View and select Show Diagram. Note that the generated diagram might not be completely accurate because it's missing the runtime information.
The following operations are available in the right-click context menu: