DVT VHDL IDE User Guide
Rev. 21.1.24, 8 June 2021
Many times naming conventions are established. For example each constant identifier should be written using capital letters, input ports should end with pi or each generic should not contain _.
Naming conventions are automatically checked when building a project. You just need to define them:
Right click on the project, choose Properties-> DVT -> Naming Conventions preference page.
Naming conventions can be shared using Settings Management. Managed naming conventions are not editable and are marked with gray color.
The conventions are identical if they have the same name and apply to the same language. In this case, the precedence is:
Overridden naming conventions are marked with a strike out line.
Note: If no naming_conventions.xml file is present in the project's .dvt directory, default rules will be shown. They are not enabled and will not override any rule defined in $DVT_USER_SETTINGS or $DVT_COMMON_SETTINGS.
Naming convention violations are presented as warnings in the Problems View. You can show the Problems View from menu Window > Show View > Other... > General > Problems. Double clicking on some warning will jump to the source location.
User defined naming conventions are stored in the .dvt/naming_conventions.xml file.
naming_conventions.xml file symtax
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
For example, the first convention is for VHDL, is named "MY_CONVENTION", is applicable for functions and the pattern .*_f$ (the name of the function must end with _f ) must match the name of every function, else a warning will be triggered.