DVT VHDL IDE User Guide
Rev. 21.1.31, 27 July 2021
DVT can scan simulator logs in order to extract the compilation arguments required for a project. Instead of explicitly specifying lists of files, incdirs etc., you can use one or more +dvt_init_from_simlog directives in the default.build. For example:
# Use the specified log file to identify compilation arguments; simulator will be automatically detected from the log file content
# Identify compilation arguments and compile sources based on the ius.irun simulation log file
DVT scans the specified log file and automatically identifies the simulator invocations, then creates a new file containing one or more +dvt_init sections, corresponding to the identified simulator invocation. For each +dvt_init_from_simlog directive, a corresponding default.build.from_simlog.# file is created. The .build.from_simlog.# files contain a verbatim copy of the compilation, elaboration and simulation directives that were found in the provided log file (like incdirs, top files, UVM libraries etc, design tops etc.).
By default, if no compatibility mode is specified, DVT tries to automatically detect the simulator which generated the logfile from its content. Alternatively you can specify the compatibility mode, hence forcing a particular scanning algorithm to be used, one of: ius.irun, xcelium.xrun, vcs.vlogan, vcs.vhdlan, questa.vsim and questa.vcom.
DVT eventually compiles the code using the directives in the generated files.
Tip: Log file scanning is performed using a set of built-in regular expressions. When the structure of the log file is atypical (for example using a custom simulator command name) DVT might not be able to successfully perform the scan. In such a case, you can specify one or more custom regular expression patterns using +dvt_simlog_pattern+<pattern>. Each pattern must contain a capturing group with the name 'args' containing the data to be copied in the result file.
# Specify user defined patterns
Note: If there are multiple patterns specified, the first pattern matched will be used.
Note: The compilation root is by default the parent directory of the simulation log file. To override this behavior, specify a new compilation root using +dvt_compilation_root+<path> directive.
DVT parses the log file only up to the first simulator invocation found, or until the buffer limit is reached. The buffer limit is by default 10MB, but can be modified using +dvt_simlog_buffer_max_size+<size in MB> directive.
# Specify custom buffer max size
If your log file contains multiple invocations (such as multiple compile commands) you should instruct DVT to scan the entire log file using the +dvt_simlog_full_scan directive flag to true.
# Enable full parsing
NOTE: When full scan is enabled, the +dvt_simlog_buffer_max_size has no effect.
You can specify additional directives in +dvt_init_from_simlog sections. They are copied as is in the corresponding .build.from_simlog.# file. For example: