Design and Verification Tools (DVT)

Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It is similar to well-known programming tools like Visual Studio ® , NetBeans ® , and IntelliJ ®.

DVT Eclipse allows design and verification engineers to overcome the limitations of plain code editors and use a modern and powerful tool that enables them to:

• Increase the speed and quality of new code development
• Simplify debugging and simulation analysis
• Easily understand complex or poorly documented source code
• Simplify the maintenance of legacy code and reusable libraries
• Accelerate language and methodology learning
• Improve code documentation
• Shorten project duration

The DVT IDE is built on the Eclipse Platform for easy integration within a large plug-in ecosystem. It comprises a proprietary IEEE standard-compliant parser, a smart code editor, an intuitive GUI, a comprehensive set of features that help with code inspection, navigation, documentation, and debugging and an innovative linting framework.

• On the fly standard compliant compilation. DVT includes an IEEE standard compliant parser (IEEE 1800 SystemVerilog, IEEE 1647 e Language, and IEEE 1076 VHDL). There is no need to invoke the simulator to make sure the code compiles without errors. DVT performs on-the-fly incremental compilation and as such, the editor highlights the errors in real time, as you type.
• Advanced code editing capabilities such as: autocomplete, macro expansion, intelligent code formatting, refactoring, connect module instances, code templates, and in-line reminders for task tracking.
• Code and project navigation features such as hyperlinks, semantic search, class and structural browsing (e.g. class hierarchy, design hierarchy), check and coverage views, dynamically created UML diagrams and module diagrams, and trace port connections. These features enable the users to navigate easily through tens of thousands of code lines, locate the relevant information, inspect a class or module structure, and understand the source code quickly.
• Automatic HTML documentation extraction from code comments. The documentation is always synchronized with the source code.
• Verification Methodology Support. DVT supports the Universal Verification Methodology (UVM) , Open Verification Methodology (OVM) , and Verification Methodology Manual (VMM). It includes an UVM/OVM automated compliance-checking capability and a built-in OVM-to-UVM Migration Wizard that offers advanced transition capabilities using refactoring scripts.
• Integration with the NCSim , Specman , VCS , and Questa simulators for simplified simulation analysis and debugging. One can easily invoke a simulator and then visualize and browse its output on the DVT console through a smart log viewer. The log simulation errors and warnings are hyperlinked to the problematic source code.
• Integration with revision control systems like CVS , Git , Subversion , ClearCase and bug tracking systems such as Bugzilla.
• Cross-language capabilities for mixed-language projects allows users to work with source code written in multiple languages (i.e. SystemVerilog, Verilog, VHDL, e), navigate seamlessly through large projects, easily see the big picture, and understand the whole design.
• Customizable views. Besides the source code window opened into the GUI, at any given moment one can bring in and move around the necessary information, and look from a higher perspective or drill down into details. For example, a GUI perspective can include views of the source code, types, class hierarchy, layers, errors and warnings, tasks, macros, and diagrams.

SystemVerilog is a rich object oriented programming language that provides powerful constructs and a high level of programming flexibility. Such capabilities meet the needs of today's complex design and verification requirements, but at the same time introduce new challenges in code development. For example, the possibility of implementing the same functionality in multiple ways may impact the simulation performance or lead to unexpected behavior.

The SystemVerilog compiler checks whether the source code follows the Language Reference Manual (LRM) rules. Thus, the compiler captures only language specific syntax and semantic errors. Therefore, the absence of compilation errors does not give any indication of code reliability and maintainability, or that the best coding practices have been applied. Nor it implies that compliancy with the recommended methodologies has been met.

The Verissimo SystemVerilog testbench linter is a coding guidelines and verification methodology compliance checker that enables engineers to perform an additional audit of their testbenches. With this tool they can check whether the code is free of language pitfalls and semantic or style issues, and compliant with the appropriate methodologies. Verissimo can be customized to check specific corporate coding guidelines to ensure consistency and best practices in code developing at the company level.

• Comprehensive library of generic SystemVerilog rules
• Comprehensive library of Universal Verification Methodology (UVM) checks
• Create custom rule sets by selecting from the hundreds of built-in checks
• Create new rules by using a dedicated application programming interface (API)
• Change rule severity to error, warning, or informative
• Wave hits by rule or source code location
• Annotate rules and share the notes with the team
• Generate text or HTML report
• Run both in batch and GUI modes
• Integrates with DVT