Software Tools for Efficient Code Development and Analysis in Hardware Design and Verification
Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It is similar to well-known programming tools like Visual Studio®, NetBeans®, and IntelliJ®.
DVT Eclipse allows design and verification engineers to overcome the limitations of plain code editors and use a modern and powerful tool that enables them to:
Verissimo SystemVerilog Testbench Linter performs static code analysis.
It enables engineers to perform an additional audit of their testbenches by checking whether their code
is free of language pitfalls and semantic or style issues, and compliant with the Universal Verification Methodology (UVM).
Verissimo can be customized to check specific group or corporate coding guidelines to ensure consistency and best practices
in code developing. Verissimo runs both in GUI and batch modes.
In the GUI mode, the linter integrates with the DVT Eclipse IDE.
The DVT e-Debugger Add-On it is an extended capability of the DVT Eclipse IDE,
which provides advanced debugging capabilities for the e language users
and enables them to perform debugging from the same place where they develop their code,
therefore, reducing debug flow complexity.
For example, users can easily add breakpoints, navigate the threads and call stacks,
and quickly inspect or change the variable values.
The e-Debugger add-on integrates seamlessly with Cadence® Incisive® Enterprise Simulator
to provide further productivity and quality increase in the verification process.