AMIQ EDA announced version 18.1 of its flagship solution the DVT Eclipse IDE. The new version provides System-Level Notation (SLN) support, IEEE 1801/UPF/CPF power-intent specification formats support, breadcrumb navigation capabilities, automated FPGA projects bring-up, and more.
AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports IEEE Standard 1801 and CPF Power-Intent Specification Formats
AMIQ EDA announced its Design and Verification Tools (DVT) Eclipse IDE supports the two most popular formats for describing power intent in system-on-chip (SoC) designs with multiple power domains. AMIQ support the latest releases of both formats: IEEE Std. 1801-2015 - based on the Unified Power Format (UPF) - and Common Power Format (CPF) 2.0 from the Silicon Integration Initiative (Si2).
AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports Cadence Perspec System Verifier using System Level Notation
AMIQ EDA announced its Design and Verification Tools (DVT) Eclipse IDE supports the System-Level Notation (SLN) portable stimulus syntax developed by Cadence® Design Systems, Inc. for its Perspec™ System Verifier system-on-chip (SoC) verification solution.