The Cadence® Connections® Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. Based on years of experience in re-usable verification intellectual property (VIP), the program members help you accelerate the adoption of new technologies and improve the productivity of your verification teams.
Universal Verification Methodology (UVM) is a standard to enable guaranteed development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. Accellera provides both an API standard for UVM and a reference implementation. That reference implementation is a class library defined using the syntax and semantics of SystemVerilog (IEEE 1800).