Press Releases

February 27th, 2017

San Jose, California

AMIQ EDA Releases Version 17.1 of the Design and Verification Tools Eclipse IDE

AMIQ EDA announced version 17.1 of its flagship solution the DVT Eclipse IDE. The new version provides enhanced compilation capabilities, new state machine diagrams, new source code navigation features, and more.

February 27th, 2017

San Jose, California

AMIQ EDA Introduces UVM IEEE Compliance and Migration Capabilities

AMIQ EDA announced the release of new rules for UVM IEEE Compliance checking in Verissimo and new UVM IEEE specific refactoring operations in the DVT Eclipse IDE.

February 29th, 2016

San Jose, California

AMIQ EDA Unveils New Verilog and VHDL Design-Oriented Diagrams

AMIQ EDA unveils new Verilog and VHDL design-oriented diagrams that enable both design and verification engineers to easily visualize, explore, and understand RTL code.

June 8th, 2015

San Francisco, California

AMIQ EDA Introduces Duplicate Code Detection in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA announces new rules for duplicate code detection in its Verissimo SystemVerilog Testbench Linter to help design and verification engineers improve code quality and reduce maintenance costs.

March 3rd, 2015

San Jose, California

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA announced the release of the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL, an extension to the DVT IDE that allows design and verification engineers perform debugging from the same place where they develop their code, in order to simplify and speed up debugging.

October 14th, 2014

Munich, Germany

AMIQ EDA Introduces New Capabilities in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA announced the release of new capabilities for dead code analysis and improved reporting of Pass/Fail checks in its Verissimo SystemVerilog Testbench Linter - a static code analysis tool for the SystemVerilog language and Universal Verification Methodology (UVM). The newly introduced capabilities enable engineers to further improve code performance and testbench reliability and reduce maintenance costs.

June 2nd, 2014

San Francisco, California

AMIQ EDA Launches Specador Documentation Generator for e Language, SystemVerilog, Verilog, and VHDL Projects

AMIQ EDA launches Specador Documentation Generator, a tool that automatically generates accurate HTML documentation from comments inserted in the source code, enabling design and verification engineers to effortlessly generate and maintain well-organized documentation.

March 3rd, 2014

San Jose, California

AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE

AMIQ EDA announces version 3.5 of its flagship solution - DVT Eclipse IDE. The new version provides enhanced compilation, improved UVM support, and a streamlined GUI to help design and verification engineers increase code development quality and productivity. It also offers a set of capabilities that simplifies DVT deployment.

October 24th, 2012

Bucharest, Romania

AMIQ EDA Announces Full Cross-Language Capabilities for Mixed-Language Projects

AMIQ EDA releases full cross-language capabilities for mixed-language projects in its flagship solution - Design and Verification Tools (DVT) IDE. Continuing to focus on improving productivity, AMIQ added these new capabilities to enhance cross-language integration and enable design and verification engineers to work easily on projects that include source code written in multiple languages, particularly SystemVerilog, Verilog and VHDL.

June 4th, 2012

San Francisco, California

AMIQ Releases New Design-Oriented Features in the DVT IDE

AMIQ EDA releases new design-oriented features in its Design and Verification Tools (DVT) IDE. These features enable design engineers to easily understand how a signal propagates in a design, connect two modules across the design hierarchy, and inspect and document a module structure.