Software Tools for Efficient Code Development and Analysis in Hardware Design and Verification

Verissimo SystemVerilog Testbench Linter

SystemVerilog is a rich object-oriented programming language that provides powerful constructs and a high level of programming flexibility. Such capabilities meet the needs of today's complex design and verification requirements, but at the same time introduce new challenges in code development. For example, the possibility of implementing the same functionality in multiple ways may impact the simulation performance or lead to unexpected behavior.

The SystemVerilog compiler checks whether the source code follows the Language Reference Manual (LRM) rules. Thus, the compiler captures only language-specific syntax and semantic errors. Therefore, the absence of compilation errors does not give any indication related to code reliability and maintainability. Nor it implies that best coding practices have been implemented and compliancy with the recommended methodologies has been met.

Verissimo SystemVerilog Testbench Linter is a coding guideline and verification methodology compliance checker that enables engineers to perform an additional audit of their testbenches. With this tool, users can check whether their code is free of language pitfalls and semantic or style issues, and compliant with the appropriate methodologies. Verissimo can be customized to check specific group or corporate coding guidelines to ensure consistency and best practices in code developing.

Verissimo SystemVerilog Testbench Linter Snapshots
FEATURES
  • Comprehensive library of generic SystemVerilog and Universal Verification Methodology (UVM) built-in checks
  • Custom rule sets configuration by re-categorizing, disabling, filtering, and re-grouping built-in checks
  • API for creating new custom checks
  • Rule severity adjustment
  • Waivers for exceptions and irrelevant failures
  • Rule annotation
  • Message filtering by source, category and severity
  • Text or HTML analysis reports
  • Batch or GUI mode
  • Integration with the DVT Eclipse IDE (GUI mode)
5 REASONS TO CHOOSE VERISSIMO
  1. Detect and fix early in the verification process:
    • Suspicious language usage such as non-standard syntax and problematic delta cycle usage or system calls
    • Semantic issues that are not caught by the SystemVerilog compiler; for example, an overridden non-virtual method, which will likely result in an unexpected behavior
    • Improper styling like confusing declaration order and naming conventions
    • Verification methodology violations such as inappropriate object creation, missing calls, and constructs that should be avoided
  2. Create, customize, and implement group or corporate-specific rules
  3. Ensure consistency in code developing at the team or company level
  4. Enforce best coding practices
  5. Reduce code maintenance costs

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