AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports IEEE Standard 1801 and CPF Power-Intent Specification Formats
Feb 26, 2018, San Jose, California — AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis, today announced its Design and Verification Tools (DVT) Eclipse IDE supports the two most popular formats for describing power intent in system-on-chip (SoC) designs with multiple power domains. AMIQ support the latest releases of both formats: IEEE Std. 1801-2015 - based on the Unified Power Format (UPF) - and Common Power Format (CPF) 2.0 from the Silicon Integration Initiative (Si2).
Many SoC designs must meet low-power requirements for reasons of battery life, thermal control, and governmental regulations. One common technique is designing different portions of the chip (power domains) to run at different power levels and to turn on and off independently. These decisions are typically made at the architectural level. A power-intent specification captures the desired behavior and enables verification that the design implementation matches this behavior.
An IEEE Std. 1801 or CPF specification is a file distinct from the design description. This separates the intent from the implementation but means that it is very easy for the two descriptions to get out of synchronization as the design evolves. Module and signal renames as well as changes in the design hierarchy can render the power-intent file outdated and cause verification errors. DVT Eclipse IDE solves this problem by reading in both descriptions and cross-checking them. Every time a change is made, the code is compiled instantly and the checks are updated automatically.
DVT Eclipse IDE automatically assigns a color to each power domain and uses this color scheme to visually correlate the domains in views of the power intent file, the design description, the design hierarchy browser, and automatically generated design schematics. Hyperlinks make it easy to navigate between these views within a selected power domain. Any inconsistency between intent and implementation is detected immediately and appropriate debug information is displayed.
“The introduction of power-intent formats was a major step in helping SoC teams verify their low-power design features,” said Cristian Amitroaie, CEO of AMIQ EDA. “The new support in DVT Eclipse IDE makes it much easier to design and verify these features. Engineers writing IEEE Std. 1801 or CPF now have the same benefits as users of other languages that DVT Eclipse IDE supports, including SystemVerilog, VHDL, e and C/C++.”
Availability and Pricing
Support for power intent is available today via DVT Eclipse IDE. Demonstrations and more information will be available at DVCon US 2018, February 26-28, in San Jose, Calif. AMIQ EDA will exhibit in Booth #405 and will showcase all its products: DVT Eclipse IDE, DVT Debugger, Verissimo SystemVerilog Testbench Linter and Specador Documentation Generator.
Pricing is available upon request.
About AMIQ EDA
AMIQ EDA provides design and verification engineers with platform-independent software tools that enable them to increase the speed and quality of new code development, simplify debugging and legacy code maintenance, accelerate language and methodology learning, improve testbench reliability, extract automatically accurate documentation, and implement best coding practices. Its solutions, DVT Eclipse IDE, DVT Debugger, Verissimo SystemVerilog Testbench Linter, and Specador Documentation Generator have been adopted worldwide. AMIQ strives to deliver high quality solutions and customer service responsiveness. For more information about AMIQ EDA and its solutions, visit www.amiq.com and www.dvteclipse.com.