Software Tools for Efficient Code Development and Analysis in Hardware Design and Verification
Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It is similar to well-known programming tools like Visual Studio®, NetBeans®, and IntelliJ®.
DVT Eclipse allows design and verification engineers to overcome the limitations of plain code editors and use a modern and powerful tool that enables them to:
DVT Debugger Add-On Module
The DVT Debugger Add-On Module it is an extended capability of the DVT Eclipse IDE,
which provides advanced debugging capabilities for the e language, SystemVerilog, Verilog and VHDL users
and enables them to perform debugging from the same place where they develop their code,
therefore, reducing debug flow complexity.
For example, users can easily add breakpoints, navigate the threads and call stacks,
and quickly inspect or change the variable values.
The DVT Debugger integrates seamlessly with major simulators
to provide further productivity and quality increase in the verification process.
Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows verification engineers to accurately identify improper SystemVerilog language, semantics, and styling usage, as well as unused code elements, verification methodology violations, and performance issues. It helps improve testbench code reliability and maintainability and implement best coding practices.
Verissimo runs both in batch and GUI modes and can be customized to check specific coding guidelines to meet the demands of small teams up to larger verification groups or global companies.
Its HTML reporting capabilities include a dashboard that summarizes linting results, provides advanced searching and filtering capabilities, bookmarking and monitoring features.
Specador is a tool that automatically generates accurate HTML documentation from comments inserted in the source code. It works in batch mode (command line) and uses dedicated language parsers.
The tool enables design and verification engineers to effortlessly generate and maintain proper and well-organized documentation.
With Specador, users can generate meaningful documentation of a design or verification environment even from poorly documented source code,
because Specador compiles the code and can generate cross-linked class inheritance trees, design hierarchies, and diagrams.