Verissimo SystemVerilog Testbench Linter User Guide
Rev. 18.1.32, 12 October 2018

4.9 All Build Directives

Directive Note Description
-ams In dvt and vcs.vlogan compatibility modes: enables Verilog AMS 2.3 extended syntax for Verilog/SystemVerilog files.


In questa.vlog compatibility mode: enables wreal extended syntax for Verilog/SystemVerilog files.


In ius.irun compatibility mode: all files that would be parsed with a Verilog / VHDL syntax flavor will be parsed with Verilog AMS 2.3 / VHDL AMS 1999 instead. Has precedence over other syntax specifications.
-amscompilefile "file:<file_path>[ ...]"ius.irun Compatibility Mode-SpecificEquivalent with specifying <file_path> as a top file.
-asext <ext>[,<ext>]ius.irun Compatibility Mode-SpecificEquivalent to -as_ext +<ext>[,<ext>]
-CFLAGS


-ccflags


-ccargs


-I -D -L -l -imacros -include
GLOBAL


SystemVerilog Only
Gcc arguments used by DVT to configure the CDT builder.
-ccext <ext>ius.irun Compatibility Mode-SpecificEquivalent to -c_ext +<ext>[,<ext>]
-cxxext <ext>ius.irun Compatibility Mode-SpecificEquivalent to -cpp_ext +<ext>[,<ext>]
-cuname <compilation_unit_name> Compile under <compilation_unit_name> package; the directive is enforced until:


* another -cuname directive is encountered


* +dvt_init directive is encountered


* end of default.build is encountered
-default_ext <syntax>ius.irun Compatibility Mode-SpecificSet the Language Syntax for Unmapped Extensions. See ius.irun Compatibility Mode for more details regarding the <syntax> argument.
+define+<DEFINE_NAME>=<replacement>


-define <DEFINE_NAME>=<replacement>
 Define a preprocessing define; the replacement is optional; you may quote the replacement with ' or "; if defined, environment variables are expanded.
+dvt_active_test+<path>e Language OnlyThe definition of structs/units/types declared in several Test Files is considered to be the one in the Active Test File.
+dvt_auto_link+<true/false>GLOBALEnable automatic linking of resources located outside the project location. Default: true.
+dvt_auto_snps_vip_macrosGLOBALGenerate and load in each invocation .dvt/auto_snps_vip_macros.svh file. It contains dummy definitions for macros which are commonly used but not defined or encrypted in Synopsis VIPs.
+dvt_auto_snps_vip_waiversGLOBALGenerate and load .dvt/auto_snps_vip_waivers.xml file. It contains waivers for problems commonly encountered when working with encrypted Synopsis VIPs.
+dvt_auto_link_file+<path/to/file>GLOBALAuto-link the specified file.
+dvt_auto_link_root+<alias>=<root_path>GLOBALWhen Auto-Linking


<root_path>/subpath/to/file


link it as


DVT Auto-Linked/<alias>/subpath/to/file


This directive helps to reduce the depth of the virtual filesystem hierarchy under DVT Auto-Linked, because the <root_path> sequence of virtual folders is compacted to <alias> virtual folder. The <root_paths> and <aliases> specified like this must be unique, and therefore only the first occurrence is considered. This is a global directive. Aliases may not be names of directories located directly under the filesystem root (like for example etc or bin).
+dvt_autoconfig_quartus_project_revision+<revision_name>SystemVerilog and VHDL onlyUse <revision_name>.
+dvt_autoconfig_disable_quartusSystemVerilog and VHDL onlyIgnore Quartus project configuration files and fallback to default auto-config.
+dvt_autoconfig_disable_xilinxSystemVerilog and VHDL onlyDisables auto-config from Xilinx ISE/Vivado project. Fallback to default auto-config.
+dvt_autoconfig_ise_xise+<xise_file_name>SystemVerilog and VHDL onlyAuto-config from ISE project using the <xise_file_name> file.
+dvt_autoconfig_quartus_script_location+<script_file_path>SystemVerilog and VHDL onlyFor debugging purposes. Use <script_file_path> to analyze Quartus project configuration files.
+dvt_autoconfig_timeout+<timeout_seconds> Interrupt build if project autoconfiguration takes more than the specified threshold (in seconds). Set 0 to disable timeout. Default: 40 seconds.
+dvt_autoconfig_vivado_sim_fileset+<fileset_name>SystemVerilog and VHDL onlyAuto-config from Vivado project using the <fileset_name> fileset.
+dvt_build_log_file_location+<path_to_existing_directory>GLOBALSpecify the location of the internal builder log file. Default: ./ (Project location).
+dvt_build_log_to_console+<true/false>GLOBALEnable/disable internal builder logging to console. Default: true.
+dvt_build_log_to_file+<true/false>GLOBALEnable/disable internal builder logging to file. Default: true.
+dvt_cpf+<cpf_file>SystemVerilog and VHDL OnlySpecify a CPF file for compilation.
+dvt_compilation_root+</path/to/compilation/root> Specify the compilation root. Relative paths specified in default.build will be resolved as relative to this location, except for the special cases that rise when Including Other Argument Files.
+dvt_db_location+<path>GLOBALSave the project database files under <path>/dvt_db/<project_name> directory. The <path>/dvt_db/<project_name> directory will be created if needed and may be overwritten at each full/incremental project build. In certain situations (for example if write access for <path>/dvt_db/<project_name> is denied or the directory is in use by another DVT instance) DVT falls back to the default location: <dvt_workspace>/.metadata/.plugins/org.eclipse.core.resources/.projects/<project_name>.
+dvt_define_system_function+<function1_name>+<function2_name>+...SystemVerilog OnlyDefine System Verilog system functions with the provided names.
+dvt_define_system_task+<task1_name>+<task2_name>+...SystemVerilog OnlyDefine System Verilog system tasks with the provided names.
+dvt_disable_parallel_lex_parseGLOBAL


SystemVerilog Only
Disable lexing-parsing parallelization.
+dvt_disable_preproc_optimize+<true/false>GLOBAL


SystemVerilog Only
Disable DVT preprocessing optimizations. Default: false.
+dvt_disable_rtl_checks


GLOBAL


SystemVerilog and VHDL Only
Disable the RTL specific semantic checks: SENSITIVITY_MISSING/SENSITIVITY_UNUSED and SIGNAL_NEVER_READ/SIGNAL_NEVER_WRITTEN/SIGNAL_NEVER_USED. By default the checks are enabled.
+dvt_disable_checks+<check_id1>+<...>DEPRECATED


GLOBAL


SystemVerilog and VHDL Only
Disable a set of semantic checks by ID.


For example: +dvt_disable_checks+UNDECLARED_IDENTIFIER


Possible check IDs: UNDECLARED_IDENTIFIER (SystemVerilog and VHDL), CONTINUOUS_ASSIGNS (SystemVerilog), INSTANCES_AND_PORT_CONNECTIONS (SystemVerilog and VHDL), REDUNDANT_OTHERS_CHOICE (VHDL), MISSING_OTHERS_CHOICE (VHDL). By default no checks are disabled.
+dvt_disable_uvm_reuseGLOBAL


SystemVerilog Only
Compile the UVM package in every invocation which specifies -uvm / -ntb_opts uvm. By default UVM is compiled only in the first invocation, and subsequent -uvm / -ntb_opts uvm only provide the UVM incdir. Default value: false
+dvt_disable_naming_convention_checks


GLOBAL


e Language and VHDL Only
Disable naming convention checks. Default value: false
+dvt_e_enable_non_standard_checks+<true/false>GLOBAL


e Language Only
Enable/disable non-standard syntax and semantic checks. Default: false.
+dvt_e_sn_which_emulationGLOBAL


e Language Only
Use the following set of search paths to locate VIPs\n instead of sn_which.sh:


/


<IUS Install Location>/specman/linux/


<IUS Install Location>/specman/src/


<IUS Install Location>/specman/docs/


<IUS Install Location>/specman/tcl/specman/


<IUS Install Location>/specman/linux/


<IUS Install Location>/specman/src/


<IUS Install Location>/specman/docs/


<IUS Install Location>/specman/tcl/specman/


<IUS Install Location>/specman/erm_lib/


<IUS Install Location>/specman/sn_lib/


<IUS Install Location>/specman/packages/


<IUS Install Location>/specman/uvm/uvm_lib/


<IUS Install Location>/specman/ovm/ovm_lib/


<IUS Install Location>/specman/erm_lib/


<IUS Install Location>/specman/sn_lib/


<IUS Install Location>/specman/packages/


<IUS Install Location>/specman/uvm/uvm_lib/


<IUS Install Location>/specman/ovm/ovm_lib/
+dvt_e_macro_strict_exp_checking+<true/false>GLOBAL


e Language Only
If true, the <exp> match expression will match only valid expressions. If false, <exp> is equivalent with the <any> match expression that matches any non-empty sequence of characters. Default: false.
+dvt_e_macro_exp_back_tracking+<true/false>GLOBAL


e Language Only
If true, the parser will reject a user defined expression match if the result of the macro reparse is not a valid expression. Default: true.
+dvt_e_sn_extract_defines+<true/false>GLOBAL


e Language Only
Automatically extract and define the Specman version defines. Default: true.
+dvt_e_sn_which_add+<vip1>+<vip2>+...


+dvt_e_sn_which_clear
GLOBAL


e Language Only
By default, the following VIPs are located using sn_which.sh, and their locations are added to the $SPECMAN_PATH: evc_util, vr_ad, ovm_e, uvm_e. When an irun installation newer than 13.10 is detected, only evc_util, vr_ad, and uvm_e are added. Use +dvt_sn_which_add+<vip1>+<vip2>+... to add to this list and +dvt_sn_which_clear to clear it.
+dvt_enable_non_top_instances_check+<true/false>GLOBAL


SystemVerilog Language Only
Enables analysis of all modules/instances when using -top/+nctop+ directive. The modules/instances that are not children of the top s are not resolved (semantic errors/warnings are not reported) unless this variable is set to true. Default: false.
+dvt_enable_unknown_directive_warnings+<true/false>GLOBALTrigger warnings for unknown build directives. Default: false.
+dvt_ext_map+<syntax>+<ext> Files with <ext> extension are parsed using the specified <syntax>. See Default DVT Compatibility Mode for more details regarding <syntax>.
+dvt_ext_unmap+<ext> Files with <ext> extension are parsed using the Language Syntax for Unmapped Extensions.
+dvt_ext_unmap_all All files are parsed using the Language Syntax for Unmapped Extensions.
+dvt_ext_unmapped_syntax+<syntax> Set the Language Syntax for Unmapped Extensions. See Default DVT Compatibility Mode for more details regarding <syntax>.
+dvt_extract_comment_above+<true/false>GLOBAL


SystemVerilog and VHDL Only
Extract comments above elements. Default: true.
+dvt_extract_comment_above_max_empty_lines+<number_of_lines>GLOBAL


SystemVerilog and VHDL Only
Extract comment if located at no more than specified number of empty lines above element declaration. Default: 1.
+dvt_extract_comment_bcd+<true/false>GLOBAL


SystemVerilog and VHDL Only
Extract /** begin comment delimiter comments. Default: true.
+dvt_extract_comment_header+<true/false>GLOBAL


SystemVerilog and VHDL Only
Extract file header comments and associate them with the first element in file (module, entity etc.). Default: false.
+dvt_extract_comment_inline+<true/false>GLOBAL


SystemVerilog and VHDL Only
Exctract comments inline with elements. Default: true.
+dvt_extract_comment_ml+<true/false>GLOBAL


SystemVerilog and VHDL Only
Extract /* multi line comments. Default: true.
+dvt_extract_comment_sl+<true/false>GLOBAL


SystemVerilog and VHDL Only
Extract // single line comments. Default: true.
+dvt_file_compile_timeout+<timeout>GLOBALDuring full compilation, skip parsing a file if it takes more than the specified threshold (in seconds). Set 0 to disable timeout. Default: 40 seconds.
+dvt_file_substitute+<file_path>=<substitute_file_path>GLOBAL


SystemVerilog and VHDL Only
During compilation, the <file_path> file will be substituted with the <substitute_file_path> file.
+dvt_full_compile_checks+<scope>GLOBAL


SystemVerilog and VHDL Only
In order to speed-up full compilation, you may chose to fully check only a relevant subset of your source code. This directive controls the scope of the full build checks:


+dvt_full_compile_checks+FULL - all of the code is checked


+dvt_full_compile_checks+LIBS+lib1+lib2 - only the specified libraries are checked, some basic checks are still performed for the rest of the code


+dvt_full_compile_checks+NOT_LIBS+lib1+lib2 - all of the code is checked except for the specified libraries, where only some basic checks are performed


+dvt_full_compile_checks+PKGS+lib1::pkg1+lib2::pkg2 - only the specified packages are checked, some basic checks are still performed for the rest of the code


+dvt_full_compile_checks+NOT_PKGS+lib1::pkg1+lib2::pkg2 - all of the code is checked except for the specified packages, where only some basic checks are performed


+dvt_full_compile_checks+OFF - only some basic checks are performed


Default: FULL
+dvt_gcc+</path/to/gcc_executable>GLOBALSpecify location of GNU C compiler executable.
+dvt_gcc_link_system_headersGLOBALEnable automatic linking of C system headers. Default: false.
+dvt_gcc_timeout+<timeout>GLOBALTimeout in seconds when running GCC. Set 0 to disable timeout. Default: 40 seconds.
+dvt_hdtvGLOBAL


SystemVerilog Only
Hide duplicates from Types, Checks and Coverage Views.
+dvt_incremental_compile_checks+<scope>GLOBAL


SystemVerilog and VHDL Only
In order to speed-up incremental compilation, you may chose to turn off advanced checking.


+dvt_incremental_compile_checks+OFF - only some basic checks are performed all over the code


+dvt_incremental_compile_checks+ON - checks are performed in all affected areas of your code that are also checked at full build (see +dvt_full_compile_checks)


Note: if +dvt_full_compile_checks is set to OFF this flag has no effect.


Default: ON
+dvt_incremental_compile_max_lines+<max_lines_number>GLOBALFiles with more than max lines will not be incrementally compiled. Set 0 for infinite limit. Default: 15000.
+dvt_incremental_compile_timeout+<timeout>GLOBALDuring incremental compilation, skip the file if parsing or semantic checking takes more than the specified threshold (in seconds). Set 0 to disable timeout. Default: 4 seconds.
+dvt_init[+<compat_mode>] Equivalent of a new invocation, resets all directives except for the GLOBAL ones. See Compatibility Modes for a detailed description.
+dvt_init_auto[+<compat_mode>] Automatically identify and compile all the source files in the compilation root. The compilation root defaults to the project directory and can be changed using +dvt_compilation_root+ directive. If a compatibility mode is not specified, it defaults to dvt. See Auto-config for a detailed description.
+dvt_init_xilinx[+<lib1>+<lib2+...>] Compile the specified libraries from the $DVT_XILINX_HOME installation. Similar with +dvt_init, it is equivalent with a new invocation. The available libraries are UNISIM, UNIMACRO, UNIFAST, XILINXCORELIB, CPLD, SIMPRIM, SECUREIP_VER, UNISIMS_VER, UNIFAST_VER, UNIMACRO_VER, SIMPRIMS_VER, XILINXCORELIB_VER, UNI9000_VER, CPLD_VER, RETARGET. See Xilinx Libraries Compilation for a detailed description.
+dvt_init_uvvm Compile the UVVM sources. Similar with +dvt_init, it is equivalent with a new invocation.
+dvt_init_uuvm_vvc Compile the UVVM_VVC sources. It should be used for every VVC. Similar with +dvt_init, it is equivalent with a new invocation.
+dvt_init_osvvm Compile the OSVVM sources. Similar with +dvt_init, it is equivalent with a new invocation.
+dvt_max_nof_threads+<num_threads>GLOBALConfigure the maximum number of threads to use during different phases of intensive computation (e.g. semantic checking, etc.). Default: 8
+dvt_path_pattern_timeout+<timeout> Timeout in seconds when scanning path patterns (like for example /**/*.v). Default: 5.
+dvt_pf_debugSystemVerilog and VHDL OnlyPrint debug information during power format build phase.
+dvt_prepend_initGLOBALYou can use a +dvt_prepend_init section to specify directives like +define, +dvt_setenv, +incdir etc. that are prepended to all +dvt_init sections. All directives between +dvt_prepend_init and the next +dvt_init will be "copied" in all subsequent +dvt_init sections.
+dvt_preprocess_translate_pragmas+<pragma1>+<pragma2>+...SystemVerilog and VHDL OnlyInstructs DVT to skip analyzing the code between pragmas such as


// <pragma> translate_off


// <pragma> translate_on


You can specify any number of pragmas as arguments to this directive, separated by '+' like for example


+dvt_preprocess_translate_pragmas+pragma+synopsys+synthesis


' Note:' In VHDL, the code background will be highlighted, but it will still be analyzed.
+dvt_pss_cppAdd $PSS_CPP_HOME/include/pss.h as topfile and $PSS_CPP_HOME/include as C include dir. Falls back to $DVT_PSS_CPP_HOME if $PSS_CPP_HOME is not defined. 
+dvt_pverilog_ext_map+<(p) files extension>=<(g) files extension>GLOBAL


SystemVerilog Only
Map extensions of PVerilog files to extensions of generated Verilog files. For example:\n +dvt_pverilog_ext_map+.svp=.sv
+dvt_pverilog_comment_map+"<regex_pattern>"GLOBAL


SystemVerilog Only
Infer mapping from generated files, assuming they contain a comment pointing to the corresponding PVerilog source file. Specify a regular expression pattern containing a named capturing group called PFILE. The pattern is applied to all comments at full build time. For example:


+dvt_pverilog_comment_map+"Source file: (?<PFILE>\S+)"
+dvt_pverilog_comment_map_debugGLOBAL


SystemVerilog Only
Turn on debugging for +dvt_pverilog_comment_map. Pattern match information will be printed in the build console. You can also specify a string to test the patterns against. For example:


+dvt_pverilog_comment_map_debug+"Source file: /path/to/file.vp"
+dvt_pverilog_path_map+<path prefix of (p) files>=<path prefix of (g) files>GLOBAL


SystemVerilog Only
Map root path of PVerilog files to root path of generated Verilog files. For example:\n +dvt_pverilog_path_map+${PREPROCESS_SOURCE}=${PREPROCESS_TARGET}
+dvt_pverilog_run_on_save+"RUN_CONFIG_NAME"GLOBAL


SystemVerilog Only
Specify the name of the run configuration to be executed when you save the PVerilog file in the PVerilog editor p or c tabs.


Within the run configuration, use ${selected_resource_loc} variable to refer to the path of the PVerilog file.
+dvt_semantic_checks_timeout+<timeout>GLOBAL


SystemVerilog and VHDL Only
Popup semantic checking dialog asking to continue or stop when full compilation semantic checking takes more than the specified timeout (in seconds). Default value: 30.
+dvt_setenv+<NAME>[=VALUE] Define an environment variable. Its value is visible for subsequent directives and during parsing.
+dvt_skip_compile+<simple_pattern> Instructs DVT to skip analyzing the files whose absolute path matches the specified <simple_pattern>. In a simple pattern you can use wildcards such as '*' (any string) and '?' (any character). Such skipped files are decorated distinctively in the Navigator View:
.
+dvt_skip_compile+not+<simple_pattern> Instructs DVT to skip analyzing the files whose absolute path does not match the specified <simple_pattern>. In a simple pattern you can use wildcards such as '*' (any string) and '?' (any character). Such skipped files are decorated distinctively in the Navigator View:
.
+dvt_skip_compile+regex+<regex_pattern> Instructs DVT to skip analyzing the files whose absolute path matches the specified <regex_pattern>. Such skipped files are decorated distinctively in the Navigator View:
.
+dvt_skip_compile+regex+not+<regex_pattern> Instructs DVT to skip analyzing the files whose absolute path does not match the specified <regex_pattern>. Such skipped files are decorated distinctively in the Navigator View:
.
+dvt_skip_ext+<ext> Do not parse top files with <ext> extension. The dot (.) for specifying <ext> is optional. For example +dvt_skip_ext+.gv and +dvt_skip_ext+gv are equivalent.
+dvt_skip_protected_code+trueGLOBAL


SystemVerilog Only
Do not analyze code encolsed in `protect ... `endprotect pragmas.
+dvt_systemcAdd $SYSTEMC_HOME/src/systemc.h as topfile and $SYSTEMC_HOME/src as C include dir. Falls back to $DVT_SYSTEMC_HOME if $SYSTEMC_HOME is not defined. 
+dvt_test+<path>e Language OnlySpecify a top file and mark it as test. For example, the e Language test files have a special status, see e Language Test Files.
+dvt_upf+<upf_file>SystemVerilog and VHDL OnlySpecify a UPF file for compilation.
+dvt_undefine+<DEFINE_NAME>SystemVerilog OnlyUndefines <DEFINE_NAME> preprocessing symbol. Equivalent with `undef <DEFINE_NAME>. The +dvt_undefine directives are applied on top of all other specified +defines. Ordering relative to other specified top files is relevant.
+dvt_wrealSystemVerilog OnlyEnables wreal extended syntax for Verilog/SystemVerilog files.
-extincludevcs.vlogan Compatibility Mode-SpecificThe included files are parsed using the syntax as specified by directives, that is using by ext syntax (if explicit) or the syntax for unmapped extensions. It overrides the default behavior.
+incdir+<path>


-incdir <path>
SystemVerilog OnlyIndicate search directories for files included with `include preprocessing directive.
+libext+<ext1>+<ext2>+<extN>


-libext <ext1>,<ext2>,<extN>
SystemVerilog Only


-libext is ius.irun mode specific
Specify accepted extensions for files in the library directories. Extensions must include the '.' dot character.


In ius.irun compatibility mode, either plus '+' or comma ',' may be used as extension list separator for either directive.


Note: there are no default extensions, .v and .sv don't have a special status.
-libmap <path> Specify the Verilog library map file.
+librescan


-librescan
 When DVT finds an unresolved module reference in a library file or directory, it will scan for the unresolved reference starting from the first specified library; by default (librescan not specified) it starts scanning from the library that introduced the unresolved reference and continues using the specified libraries order.
-lps_1801 <upf_file>


-lps_cpf <upf_file>
ius.irun Compatibility Mode-Specific


SystemVerilog and VHDL Only
Specify a UPF or CPF power format file for compilation.
-makelib <lib_name>


-makelib /path/to/ <lib_name>


-makelib /some/path: <lib_name>


... -endlib
ius.irun Compatibility Mode-SpecificCompiles files specified inside a - makelib ... - endlib section into the <lib_name> library. Files in makelib sections are compiled before files in the enclosing invocation. Directives in the makelib section only apply to the makelib section files. Directives in the enclosing invocation apply to all files in the invocation. The - work directive is ignored within a makelib section.
+nctop+<config_name>GLOBAL


SystemVerilog Only
Specify top configuration name.
-objext <ext>ius.irun Compatibility Mode-SpecificEquivalent to -o_ext +<ext>[,<ext>]
-ovm


-uvm
 In dvt and vcs.vlogan Compatibility Modes it is equivalent with


+incdir+/path/to/xvm/src


/path/to/xvm/src/xvm_pkg.sv


where /path/to/xvm is $XVM_HOME or $DVT_XVM_HOME if $XVM_HOME is not defined, where XVM is a shorthand for OVM / UVM.


In the ius.irun and questa.vlo Compatibility Modes /path/to/xvm is automatically located within the IUS resp. Questa installation dirs. See ius.irun Compatibility Mode and questa.vlog Compatibility Mode for more details.
-ovmhome


-uvmhome
ius.irun Compatibility Mode-SpecificLoad the OVM / UVM library from the specified <path>. See ius.irun Compatibility Mode for more details.
-pa_upf <upf_file>questa.vlog and questa.vcom Compatibility Mode-Specific


SystemVerilog and VHDL Only
Specify a UPF power format file for compilation.
-realportvcs.vlogan Compatibility Mode-Specific


SystemVerilog Only
Enables wreal extended syntax for Verilog/SystemVerilog files.
-sndefine <arg>ius.irun Compatibility Mode-SpecificEquivalent to +define+<arg>
-snpath <path>ius.irun Compatibility Mode-SpecificEquivalent to +dvt_setenv+SPECMAN_PATH=$SPECMAN_PATH:<path>
-svius.irun Compatibility Mode-SpecificAll files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a Verilog syntax flavor will be parsed with SystemVerilog 2012 instead. Has precedence over -v1995.
-sv_lib <file_path>GLOBALSpecify a shared object C/C++ library. The <file_path> should be specified without the .so extension. Provided that the library contains debug info, DVT will Auto-Link the C/C++ source files from which the library was compiled. The .so extension is automatically appended to the specified path.


Implementation note: If <file_path>.so is not found, the tool will try to locate and load <file_path> instead.
-sv_liblist <file_path>GLOBALSpecify a shared object bootstrap file. The file contains a list of shared object C/C++ library paths, one per line. For each library in the bootstrap file, provided that the library contains debug info, DVT will Auto-Link the C/C++ source files from which the library was compiled. The .so extension is automatically appended to the paths specified in the bootstrap file.
-sv root <directory_path>GLOBALThe root directory path is prepended to any relative path that will be specified following this directive, using either -sv_lib or -sv_liblist or inside the shared object bootstrap file.
-sverilogvcs.vlogan Compatibility Mode-SpecificSets the syntax for unmapped extensions to SystemVerilog. This directive has precedence over +v2k.
-<syntax>_ext [+]<ext>[,<ext>]ius.irun Compatibility Mode-SpecificFiles with <ext> extension will be parsed using the specified <syntax>. If the optional + is specified, the mapping will be added to the default File Extension to Language Syntax Mapping. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default File Extension to Language Syntax Mapping will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - vlog_ext .svh,.svp. The dot (.) for specifying <ext> is mandatory.


The following directives are supported: -a_ext, -amsvhdl_ext, -amsvlog_ext, -as_ext, -c_ext, -cpp_ext, -dynlib_ext, -e_ext, -o_ext, -spice_ext, -sysv_ext, -vhcfg_ext, -vhdl_ext. See ius.irun Compatibility Mode for more details regarding <syntax>.
+systemverilogext+<ext>vcs.vlogan Compatibility Mode-SpecificAll files with <ext> extension are parsed using the SystemVerilog syntax.
-top <config_name>GLOBAL


SystemVerilog Only
Specify top configuration name.
+UVM_TESTNAMEGLOBALThe name of the UVM test which will be automatically created under uvm_root.
-upf <upf_file>vcs.vlogan and vcs.vhdlan Compatibility Mode-Specific


SystemVerilog and VHDL Only
Specify a UPF power format file for compilation.
-v <path> Specify a Verilog library file.
-v1995


-v95
ius.irun Compatibility Mode-SpecificAll files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with Verilog 2001 will be parsed instead with a reduced keywordset variant of Verilog 2001. The reduced keywordset does not contain the keywords automatic, localparam, generate, endgenerate, and genvar.
-v200xius.irun Compatibility Mode-SpecificAll files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 2000 instead. Has precedence over -v93.
-v93ius.irun Compatibility Mode-SpecificAll files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 93 instead.
+v2kvcs.vlogan Compatibility Mode-SpecificSets the syntax for unmapped extensions to Verilog 2001.
+verilog1995ext+<ext>vcs.vlogan Compatibility Mode-SpecificAll files with <ext> extension are parsed using the Verilog 1995 syntax.
+verilog2001ext+<ext>vcs.vlogan Compatibility Mode-SpecificAll files with <ext> extension are parsed using the Verilog 2001 syntax.
-vhdl87vcs.vhdlan Compatibility Mode-SpecificSets the syntax for unmapped extensions to VHDL 1076-1987.
-vhdlext <ext>ius.irun Compatibility Mode-SpecificEquivalent to -vhdl_ext +<ext>[,<ext>]
-vlogext <ext>ius.irun Compatibility Mode-SpecificEquivalent to -vlog_ext +<ext>[,<ext>]
-w <lib>


-work <lib>
vcs.vhdlan Compatibility Mode-SpecificCompile intro library <lib>.
-work <lib> Compile into library <lib>.
-wreal <res_func>vcs.vlogan Compatibility Mode-Specific


SystemVerilog Only
Enables wreal extended syntax for Verilog/SystemVerilog files.
-y <path> Specify a Verilog library directory.
-pkgsearch <lib>ius.irun Compatibility Mode-Specific


SystemVerilog Only
Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
-liblist <lib1>[+<lib2>+...]vcs.vlogan Compatibility Mode-Specific


SystemVerilog Only
Specify the library search order for Verilog packages.

NOTE: GLOBAL directives are effective for all invocations. They are not reset by +dvt_init directives.