Verissimo SystemVerilog Testbench Linter User Guide
Rev. 18.1.18, 15 June 2018

4.1 Auto-config

Particularly for small projects, in order to simplify project configuration, instead of explicitly specifying lists of files, incdirs etc., you can use one or more +dvt_init_auto directives in For example:

// Identify and compile sources from the project directory

// Identify and compile sources from some other path

DVT scans the specified directories and automatically detects how to compile the source code files. For each +dvt_init_auto directive, a corresponding file is created. The files contain compilation directives like incdirs, top files, libraries, UVM libraries, Xilinx libraries, etc. resulting from the auto-configuration algorithm. After scanning, DVT compiles the code using the directives in generated auto files.

DVT automatically detects and analyzes existing Intel(Altera) Quartus or Xilinx ISE/Vivado projects in the compilation root directory of a +dvt_init_auto directive. For more details see FPGA Support.

NOTE: Auto files are overwritten on every full build.

You can specify additional directives in +dvt_init_auto sections. They are copied as is in the corresponding file. For example:


You can specify a compatibility mode and use simulator specific directives:


The available compatibility modes are: dvt, ius.irun, vcs.vlogan and vcs.vhdlan. If a compatibility mode is not specified, it defaults to dvt. See Compatibility Modes for a detailed description.

TIP: When working with large filesystem hierarchies or slow network drives, the scan phase might time out, by default after 40 seconds. To increase the timeout for a particular +dvt_init_auto section, use +dvt_autoconfig_timeout build config directive. For example to set timeout to 2 minutes: