DVT IDE for VS Code SystemVerilog User Guide

Rev. 24.1.9, 26 April 2024

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Installation
- System Requirements
- Install DVT for VS Code from Marketplace
- Install DVT for VS Code from VSIX
- Install DVT for VS Code Using a Pre-Packed Distribution
- Set the License
User Interface
- VS Code User Interface
- DVT IDE for VS Code User Interface
  - Editor
  - Activity Bar
  - Side Bar
  - Status Bar
  - Panel
Predefined Projects
Build Configurations
- Project Natures
- Non-top files
- default.build
- Auto-config
- Simulator Log-config
- Emulating compiler invocations
- Multiple .build Files
- Compatibility Modes
  - Default DVT Compatibility Mode
  - gcc Compatibility Mode
  - ius.irun Compatibility Mode
  - ius.perspec Compatibility Mode
  - questa.vcom Compatibility Mode
  - questa.vlog Compatibility Mode
  - questa.qrun Compatibility Mode
  - vcs.vhdlan Compatibility Mode
  - vcs.vlogan Compatibility Mode
  - xcelium.xrun Compatibility Mode
- Paths
- Strings
- Comments
- Environment Variables
- Including Other Argument Files
- Build Persistence
- All Build Directives
- SystemVerilog OVM or UVM Library Compilation
- Xilinx Libraries Compilation
- Intel(Altera) Quartus Libraries Compilation
- Questa Libraries Compilation
- Use of External Programs
Compile Checks
- Compile Waivers
- Semantic Checks
- Synthesis Checks
- Performance Checks
- Dead Code Checks
- Non Standard Checks
Quick Fix Proposals
Content Assist (Autocomplete)
- Content Assist for CamelCase and Underscore
- Code Templates
- Module Automatic Instantiation
- Override Functions Using Autocomplete
- Implement Extern Functions Using Autocomplete
- Generate Setters and Getters Using Autocomplete
- Use Assignment Pattern for Struct Type Variable
Hyperlinks
Show Usages
Show Readers or Writers
Show Call Hierarchy
Show Type Hierarchy
Show Constraints
Show Instances
Peek Exploration
Refactoring
Override Functions
- Override Annotation
- Override Using Command Palette
- Override Using Autocomplete
Generate Setters and Getters
Code Factory
Code Formatting
- Whitespace
- Indentation
- Vertical Alignment
- Line Wrapping
- Disable Format for Code Sections
- Preferences Keys
Breadcrumb Navigation Bar
- Design Breadcrumb
- Verification Breadcrumb
- Scope Breadcrumb
Diagrams
- UML Diagrams
- Design Diagrams
- UVM Components Diagrams
- WaveDrom Timing Diagrams
- Bit Field Diagrams
  - Bit Field Diagrams for UVM registers
  - Bit Field Diagrams for packed data types
- Common Diagram Actions
- Common Diagram Toolbar
Syntax Coloring
Tooltips
- Comments Formatting
  - Javadoc
  - Natural Docs
Workspace Symbols
Views
- Compile Order View
  - Build Config Hierarchy
- Compiled Files View
- Config DB View
- Design Hierarchy View
- Diagnostics View
- Factory Overrides View
- Outline View
- Problems View
- Registers View
- Verification Hierarchy View
Quick Search in Views
- CamelCase
- Simple Regex
- Hierarchical Search
- Search for Members
- Search Port in Design Hierarchy
- Search Port in Verification Hierarchy
Content Filters
- Content Filters XML Syntax
- Filtering by Element Type
- Content Filters Examples
- Predefined Content Filters
Macros Support
- Inactive Code Highlight
- Macro Expansion
Inactive Generates Code Highlight
Database Out of Sync Notification
External Tools Integration
UVM Support
- UVM Runtime Elaboration
- Runtime UVM Configuration Queries
- UVM Content Filters
- UVM Sequence Tree
- UVM Templates
- UVM Verification Hierarchy
Scripts
- dvt_code.sh
  - dvt_code.sh Syntax
  - dvt_code.sh Examples
- dvt_ls.sh
  - dvt_ls.sh Syntax
  - dvt_ls.sh Examples
Custom Scripts
SCM Checkout Hook
Memory Monitor
> Application Notes
- Flow Integration
- Environment Variables
- Design Elaboration
- Compilation Speed-up
- Precompilation Support
- Encrypted VIP Support
- FPGA Support
  - Intel(Altera) Quartus
    - Intel(Altera) Quartus Libraries Compilation
  - Xilinx ISE/Vivado
    - Xilinx Libraries Compilation
- Preprocessed Files Support
- Output and logging
Handy VS Code Documentation Pointers
What is New?
How to Report an Issue?
Legal Notices
Third Party Licenses
Q & A
- Can I deactivate DVT support for a workspace even though one of my workspace folders contains a .dvt directory?

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Chapter 38. Application Notes

Table of Contents

38.1. Flow Integration

38.2. Environment Variables

38.3. Design Elaboration

38.3.1. Top candidates
38.3.2. Parameter values
38.3.3. Unelaborated Design
38.3.4. Debugging
38.3.5. Performance

38.4. Compilation Speed-up

38.5. Precompilation Support

38.6. Encrypted VIP Support

38.7. FPGA Support

38.7.1. Intel(Altera) Quartus
38.7.2. Xilinx ISE/Vivado

38.8. Preprocessed Files Support

38.9. Output and logging

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