DVT IDE for VS Code SystemVerilog User Guide
Rev. 23.1.8, 29 March 2023
- Installation
- Predefined Projects
- Build Configurations
- Project Natures
- Non-top files
- default.build
- Auto-config
- Simulator Log-config
- Emulating compiler invocations
- Multiple .build Files
- Compatibility Modes
- Paths
- Strings
- Comments
- Environment Variables
- Including Other Argument Files
- All Build Directives
- SystemVerilog OVM or UVM Library Compilation
- Xilinx Libraries Compilation
- Intel(Altera) Quartus Libraries Compilation
- Questa Libraries Compilation
- Use of External Programs
- Compile Checks
- Quick Fix Proposals
- Content Assist (Autocomplete)
- Hyperlinks
- Show Usages
- Show Readers or Writers
- Show Call Hierarchy
- Show Type Hierarchy
- Show Constraints
- Show Instances
- Peek Exploration
- Refactoring
- Override Functions
- Generate Setters and Getters
- Code Factory
- > Code Formatting
- Breadcrumb Navigation Bar
- Diagrams
- Syntax Coloring
- Tooltips
- Workspace Symbols
- Views
- Quick Search in Views
- Content Filters
- Macros Support
- External Tools Integration
- UVM Support
- Scripts
- Custom Scripts
- SCM Checkout Hook
- Application Notes
- Handy VS Code Documentation Pointers
- What is New?
- How to Report an Issue?
- Legal Notices
- Third Party Licenses
- Q & A
Table of Contents
In order to format a selected region of code or an entire file, use the "Format Selection" or "Format Document" commands.
All code formatting preferences are available at File > Preferences > Settings > Extensions > DVT > Text Editor > System Verilog > Formatting.