DVT SystemVerilog IDE User Guide
Rev. 21.1.1, 11 January 2021
In order to connect two module instances using new ports, you must specify the output instance (the signal source) and the input instance (the signal destination). New ports will be created across the design hierarchy as needed, in order to propagate the signal.
IMPORTANT NOTE: This feature is currently supported only in the Old Design Hierarchy View. To switch to/from the Old Design Hierarchy View, go to Window > Preferences > DVT and toggle Switch to Old Design Hierarchy View
Note 1: At any time you can change the connection output or input. Pick the direction using the radio buttons, select another instance, then right click Connect Input/Output.
Note 2: You can undo the whole refactoring operation using Undo ( Ctrl+Z).