DVT SystemVerilog IDE User Guide
Rev. 23.1.7, 15 March 2023
Sometimes a design is compiled across multiple invocations. For example, environment variables or preprocessing directives may change their values between invocations, or sources may be compiled into different libraries.
The +dvt_init+<mode> directive is equivalent with a new compiler invocation, where <mode> represents the compiler compatibilty mode. The directive resets the DVT builder to the mode specific default state and clears all the previous directives (preprocessing defines, system variables, libraries, etc.).
You may specify any number of +dvt_init directives inside a build file.
The compatibility mode is enforced until the next +dvt_init directive.
Even if there is no +dvt_init directive specified, there is always an initial reset equivalent to +dvt_init+dvt.