13.3 Vertical Alignment

When enabled, this option performs vertical alignment.

Vertical Alignment Tokens

The lines of code inside the same scope are aligned by the specified comma separated list of vertical alignment tokens.

if(a) begin       if(a) begin
x = 1;            x  = 1;   // aligned by '=' inside the if scope
xx = 1;           xx = 1;
end else begin    end else begin
xxx = 1;          xxx  = 1; // aligned by '=' inside the else scope, orthogonal to the if scope above
xxxx = 1;         xxxx = 1;
end               end

Vertical alignment is performed left to right, by the same token. For example assuming '=' and ':' as vertical align tokens:

var x : int = 1; // "first level :", "second level ="
var xx : int = 1;

a = 1; // not aligned to "second level =" above, as this is a "first level ="
aa = 1;

In order to use the comma character ',' as a vertical alignment token, the character must be preceded by the escaping character '\'.

Only consecutive lines - When enabled, only consecutive lines are vertically aligned. Two lines are consecutive if they follow each other or are separated by comment lines.

Vertical align single line comments - When enabled, single line comments are aligned.

Vertical align to open parenthesis - When enabled, vertical align to open parenthesis.

Vertical align to open curly - When enabled, vertical align to open curly.

Independent `ifdefs - When enabled, `ifdefs are independent alignment scopes:

module m0
    (
        input  [7:0] a,  // this set is not aligned with the `ifdef set
        output [7:0] bb, // c2
        `ifdef D1
            input  [7:0] a,  // this `ifdef set is indented by the indent preproc and content preference
            output [7:0] bb, // c2
        `endif
    );

Vertical Align Patterns - By Name Port Connections - When enabled, this pattern aligns instance port connections by name:

submod1 inst1(
.p1 (c1 ), // comment 1
.p22(c22[2]) // comment 2
);

Vertical Align Patterns - Class Declarations - When enabled, this pattern aligns class parameters:

class class1 #(
FIRST_PARAM_MMMMMMMMM = param_1,
SECOND_PARAM = param_2);

Vertical Align Patterns - Class Variable Declarations - When enabled, this pattern aligns class variables:

rand bit                  [15:0] addr;
rand ubus_read_write_enum        read_write;
rand int unsigned                size, a;

Vertical Align Patterns - `defines - When enabled, this pattern aligns `defines:

`define MACRO_A 5
`define ABC 3
`define CAT dog

// Different define group is aligned separately from above because of empty line above iff '''Only consecutive lines''' is on
`define FOO bar
`define BARS baz

Vertical Align Patterns - Function Declarations - When enabled, this pattern aligns function and task declarations:

task write_byte (input bit [7:0] data,
output bit error);

Vertical Align Patterns - Function Variable Declarations - When enabled, this pattern aligns function and task variable declarations:

task test_task;
    int unsigned        var_1;
    bit          [31:0] var_2;
    bit          [4:0]  var_3;
endtask

Vertical Align Patterns - Interface Port Declarations - When enabled, this pattern aligns interface ports:

interface A (
        input logic       b,   // comment
        input logic       cc,  // comment
        input logic       ddd, // comment
        input logic [7:0] eeee // comment
    );
endinterface

Vertical Align Patterns - Interface Signal Declarations - When enabled, this pattern aligns interface signals:

interface A;
    bit               has_coverage = 1; // comment
    logic             sig_bip;          // comment
    wire  logic [7:0] sig_data;         // comment
endinterface

Vertical Align Patterns - Module Port Declarations - When enabled, this pattern aligns module ports:

input         [7:0] a,      // comment
input  signed [7:0] bb,     // comment
output signed [7:0] ccc,    // comment
input               clk,    // clock
input               rst,    // reset
input               data_in // data

Vertical Align Patterns - Module Signal Declarations - When enabled, this pattern aligns module signals:

reg  signed [7:0] data_out;       // c1
wire        [1:0] byte_enable;    // c2
reg               nop;            // c3

`xvm_field macros - When enabled, this pattern aligns `xvm_field factory registration macros:

`uvm_object_utils_begin(ubus_transfer)
   `uvm_field_int    (addr,                             UVM_DEFAULT)
   `uvm_field_enum   (ubus_read_write_enum, read_write, UVM_DEFAULT)
   `uvm_field_string (master,                           UVM_DEFAULT|UVM_NOCOMPARE)
`uvm_object_utils_end