DVT SystemVerilog IDE User Guide
Rev. 19.1.17, 17 May 2019

13.5 Disable Format for Code Sections

When format is disabled, a code section is completely ignored, that is it is not formatted, nor it contributes to formatting.

  • Disable format for a code section - code sections between the @formatter:off and @formatter:on pragmas are not formatted.

   input         hclk;
   // @formatter:off
   input n_hreset;
   input hsel;
   // @formatter:on
   input [31:0]  haddr;
   input [1:0]   htrans;
   input [2:0]   hsize;
   input [31:0]  hwdata;
   input         hwrite;
   input         hready_in;

  • Disable format for a single line - lines containing the @fomatter:skip pragma inside a comment are not formatted.

   submod1 inst1(
       .p1(c1), // comment 1
       .p22(c22[2]) // comment 2
.p33(c33[3]) /* @formatter:skip */