DVT SystemVerilog IDE User Guide
Rev. 20.1.26, 30 July 2020

26.11 Extract to Module

A fragment of a module can be automatically extracted and encapsulated into a new instance.

The fragment must be a contiguous region containing only instances, always blocks and assignments.

Select the region in the editor, press Ctrl+1, select Extract to module from the list of quick assist proposals and press Enter.

The selected piece of code will be moved to a new module in a new file. Fill in the name of the new module and file.

The initial selection is replaced with an instance of the new module:

The ports of the new module are automatically computed and connected in the instantiation.

Implementation notes

  • the new file is `included on the line above the declaration of the initial module

  • signals which are not referenced anywhere outside the selection will be marked with a // FIXME after the extraction

  • currently busses are propagated through a single port even if accessed through bit selects; in such a case, a // FIXME comment can help you easily identify the unique bit selects which you might consider propagating through distinct ports

Tip: You can also right-click in the editor and go to Refactor > Extract to module to trigger this functionality.