DVT SystemVerilog IDE User Guide
Rev. 23.1.3, 31 January 2023
DVT editor marks the unelaborated generate code (i.e. generate branches that are inactive) with a colored background.
You can enable/disable the highlight and choose the highlight color: navigate to Window > Preferences then expand DVT > SystemVerilog > Editor. In the panel on the right side, you can find the Inactive generate branches group.
Note: The inactive generates code depends on the editor current design instance path shown in the Design Breadcrumb. You have the option to change the instance path, and therefore the highlight, from the Select Instance Path breadcrumb button.