DVT SystemVerilog IDE User Guide
Rev. 23.1.8, 29 March 2023
To rename an entity (type, method, macro etc.) in the source code along with all its references, place the cursor on the desired element, then right click and select Refactor > Rename (or use the shortcut combination <Shift + Alt + R>).
You will be prompted for the new name of the entity:
Click OK to perform the refactoring, or Preview to see the changes that are about to be performed in the source code. In the Preview page you can select the changes that should be performed. After you click Finish the changes are performed, and the project is rebuilt.
Tip: Matches hidden inside a macro call cannot be automatically renamed. Instead, DVT will insert a FIXME comment above the macro call to indicate that it should be refactored by hand.
Hidden matches are those matches found inside a macro call expansion, but not among the macro call parameters.
Tip: DVT can also rename matches found in JavaDoc-like annotations, such as @link, @param and @see. This feature is disabled by default, to enable it go to Window > Preferences > DVT > SystemVerilog > Refactoring and untick the Ignore JavaDoc comments box.
Tip: You can limit the scope of Rename Refactoring to the current file, see Rename in File.