DVT SystemVerilog IDE User Guide
Rev. 23.1.8, 29 March 2023
Problems are reported when a module instance does not match the module definition (has missing or extra port connections).
Place the editor cursor on a problem's line and press Ctrl + 1, select Update instance to match module definition from the list of quick fix proposals and press Enter.
The extra ports are removed and all the missing ports are added at the end of the instance port list.
Tip: You may change the newly added port connections. Press Tab key to switch between the edit boxes, and Enter when done.
Note: The quick fix only works for named port connections.