DVT SystemVerilog IDE User Guide
Rev. 23.2.28, 28 November 2023
The Registers View shows all the UVM registers within the register model hierarchy.
Open the view from the UVM menu > Show Registers. The view is populated only after setting a runtime elaborated Verification top.
By default the view content is presented as a tree rooted in the register model and comprising of register blocks, register files, and individual registers as leaves.
For each register, the view presents its name, address, access rights, associated sequencer and source code comment.
Toggle the Inspect Panel to visualize the bitfield diagram of the currently selected register.
Tip: Double click to go to the register's create call.
Tip: From the Display Mode dropdown you can switch to a flat list view, where the name represents a hierarchical path from the reg model to the reg.
Tip: You can choose the Address Radix to be Decimal or Hexadecimal.
Tip: By default the view is sorted alphabetically. Use the toolbar button to Sort by address.