DVT SystemVerilog IDE User Guide
Rev. 23.1.7, 15 March 2023
A project template is a parameterized directory tree. Both in the file contents (.v, .sv, .sh, .e, .vhd, .txt - practically any file) and in the file or directory names you can use parameters.
Combined with TODO markers, you can use a project template as a customized wizard.
Parameters are IDs surrounded by double underscores (for example __pkg_prefix__) or by x_ and _x (for example x_pkg_prefix_x).
This convention allows you to edit the template like any other project using DVT in its full power - autocomplete, hyperlinks etc. Parameters are highlighted distinctively:
NOTE: It is not mandatory (but elegant) to use DVT for template creation. It is very elegant to apply the template using DVT.
When you generate code using the project template, parameters are replaced in all files (including their names) with the values you specify:
How to generate code from a project template